Hi, the device have some kind of limitation on the usage of DMA?
What I did:
1 - Implemented DMA0 stream 0 and 1 to do the following:
DMA0 stream 0 - Update the TMR2 ARR when TMR2overflow. Generate an Event on DMA transfer.
DMA0 stream 1 - Sync with the Event generated, Update the TMR3 ARR.
This worked fine.
2 - Implemented DMA0 stream 2 and 3 to do the following:
DMA0 stream 2 - Transfer data from ADC1 to Buffer.
DMA0 stream 3 - Transfer data from ADC2 to Buffer.
Both ADC are trigger by TMR3 overflow.
This worked fine.
3 - I tried to implement the tests above together, and it does not work, TMR stopped to be updated.
4 - What is stranger if that I tried to use DMA1 stream 0 and 1 for the ADC, but it also did not work.
There is known or is some mistake I did?
The workaround was to use the TMR2 overflow interrupt to update TMR2/TMR3, and let the DMA only for the ADC's.
The board is the NUCLEO-H723ZG.
Thank you.
