Direct register write to DAC3,2,1 in F303, F334 ,F358

[mikael239955_stm1_st]

Posted on October 02, 2015 at 17:02

I want to write directly to DAC1,2,3 as i see them, DAC1 ch1, DAC1 ch2 and DAC2 ch1

as ref manual RM0316 describes, a voltage just as simple as writing to a TIM CCR is to output a voltage, like: TIM1->CCR1=120; so as DAC->DHR8R1=213; Ref manual even describes a write to DAC_DHR8R1, but such address is not defined in the stm32f30x.h file only a offset addresz. Even enable DAC1 and DAC2 is not doing anything, PA6 ,PA5 , PA4 is just floating! GPIOA->MODER |= GPIO_MODER_MODER6;                   //Set PA6 to Analog GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6;      //Set PA6 to High Speed RCC->AHBENR |= RCC_APB1ENR_DAC1EN;                   //Enable DAC1 clock RCC->AHBENR |= RCC_APB1ENR_DAC2EN;                   //Enable DAC2 clock DAC->CR |= DAC_CR_EN1;                                                //Enable DAC1 DAC->CR |= DAC_CR_EN2;                                                //Enable DAC2 There is OUTEN1 and OUTEN2 register bits but the function for these is not even described only mentioned in the register description and not defined in the 30x.h file as far as i can see but i might have become blind by reading all those convoluted  manuals! OUTEN bits are located on the same spot as buffer enable bits for DAC1 ch2 are these bits that makes PA6 5,4 floating? How do one turn on/off DAC3 buffer?Are there even a DAC3 buffer? Apparently the whole DAC thing is  tripple buffered, DHR8R1->DHR1->DOR1 and the only register one could do direct writes to is DHRyyyx, (one y to many) there is not even a block diagram over DAC3! Is this the right adress for DAC1 8 bit right aligned ( found in SPL)? #define DAC_DHR8R1_ADDRESS       0x40007410 The 303 eval dac.c mentions DAC3, this is contradictionary to RM0316 303 ref manual and 334 ref manual who dont even speak about this at all!

[raptorhal2]

Posted on October 02, 2015 at 21:33

Lets see how many hurdles I can tutor you over.

Register offsets are defined because the peripheral register set memory location may change from one device type to another. You need to look in the address map provided in the device data sheet for the base address. DAC3 does not exist for the F303. Not sure which device eval code you were looking at. Buffer enable routes the DAC output through an amplifier in the device to provide more current for lower impedance destinations. To write 12 bits to DAC Channel 1, write the value to the DAC_DHR12R1 register. The address offset is 8, but DAC1 and DAC2 will have different base addresses. Cheers, Hal

[mikael239955_stm1_st]

Posted on October 04, 2015 at 00:25

>Lets see how many hurdles I can tutor you over.

Thank you! Most appreciated! Unfortunately been looking into old ref manual version who had incomplete and faulty text and graphics. Newest version also do! Sigh!>Register offsets are defined because the peripheral register set memory location may change from >one device type to another.You need to look in the address map provided in the device data sheet >for the base address. Yes i know but this should be part of the DAC section register definition file in clear text absolute address not just an offset+base.The address in first post was a suggestion for one of the dac DHR registers.>DAC3 does not exist for the F303. Not sure which device eval code you were looking at. It actually do, 303, 328,334,373 etc but not spit out in clear text and DAC 3 is actually mentioned as DAC 3 in 303 eval.c files not consistent with ref manual (as usuall) who's current standing naming in ref manual V5 labelled as V6 on ST web page to confuse us even further. But low and be hold, page 414 clearly speaks about 3 independent 12bit dac's!>Buffer enable routes the DAC output through an amplifier in the device to provide more >current for lower impedance destinations. Not an answer to my question, rather buffer only exist for DAC1_OUT1/DAC1_channel1. Te supposed buffer 2 and 3 for DAC1_OUT2 or DAC1_channel2 and DAC2_OUT2/DAC2_channel2 is replaced by switch, so enabling DAC1 and 2 is not enough to enable the actual output of the DAC! Thank you very much ST for not mentioning this!>To write 12 bits to DAC Channel 1, write the value to the DAC_DHR12R1 register. >The address offset is 8, but DAC1 and DAC2 will have different base addresses. Point talked about in first post, DAC_DHR12R1 dont, but DHR12R1 should do but dont because PA4,5,6 is still floating no matter if enabling/disabling DAC1,2 and turning on/of OUTEN1,2 switch! ------------------------- Update to this issue: It boiled down to a faulty F334 dev board reason PA was floating , got a replacment form supplier. So working examples shown here for tripple single mode DAC's: DAC1->DHR8R1=123; DAC1->DHR8R2=123; DAC2->DHR8R1=123; 334 reference manuals is convoluted and missleading in both function and in register descriptions, 303x still do despite latest version same with F373. Example,reader get's the impression there is only one CR for all DAC channels/DAC outputs because it's described as a single DAC_CR compare this to TIM who more apropieate is described as TIMx_CCRx DAC should be described as DACx_CRx etc and not DAC_CR. Other examples from F334/303/373 manual : >The DAC integrates two output buffers that can be used to reduce the output impedance, >and to drive external loads directly without having to add an external operational amplifier. >Each DAC channel output buffer can be enabled and disabled using the corresponding >BOFFx bit in the DAC_CR register. Suddenly and contradictionary to prior manual text there is 2 buffers again, in reality not,  and it's very strange after 6 revisions that DAC_CR is still not DACx_CRx or DAC1_CR1 and DAC2_CR1 in the reference manual. so insted we have this very odd setup:. DAC1->CR |= DAC_CR_BOFF1;  //Buffer/No buffer switch prior PA4 DAC1->CR |= DAC_CR_BOFF2;  //actually OUTEN2, switch enabled prior PA5 DAC2->CR |= DAC_CR_BOFF1;  //actually OUTEN1, switch enabled prior PA6 DAC2->CR |= DAC_CR_BOFF1; who turns DAC2out1/DAC2channel1 on or off could have been for redability and clarity sake... DAC2->CR1 |= OUTEN1;

[raptorhal2]

Posted on October 04, 2015 at 19:07

Page 412 correctly identifies 4 ADCs.

Yes i know but this should be part of the DAC section register definition file in clear text abbsolute address not just an offset+base. Page 441 refers to Table 4 which, for each 3xx device, identifies the DAC 1 and 2 (and other peripherals) boundaries (base address). If they gave register definitions in absolute addresses, the result would be a mind-numbing duplication with only the addresses different, and duplicate document update effort. My life beyond the forum prevails at this time. If you are still stuck a week from now, I may be able to provide further help. Cheers, Hal

[mikael239955_stm1_st]

Posted on October 04, 2015 at 20:22

>Page 412 correctly identifies 4 ADCs.

My bad, sorry! Page 414 in RM0316 correctly identifies 3 DAC's Page 311 in RM0364 identifies 3 DAC's. >My life beyond the forum prevails at this time. If you are still stuck a week from now, I may be able to provide further help OK, thanks.. Major issue is still the floating PA4,5,6.... there might be hardware faults.... well see.

[mikael239955_stm1_st]

Posted on October 04, 2015 at 20:33

Forum engine seams to have scrambled posting order!