Diffrence between enabling Interrupt in NVIC and enabling Interrupt for Peripherie (e.g Timer)

[endy]

Posted on March 25, 2015 at 12:38

Hello!

I try to get a deeper understanding of the STM32F4 microcontrollers but there is one thing I do not really unterstand and i could�t find an answer in the literature im reading.What ist the specific difference in enabling an Interrupt for the NVIC and for the Peripherie? I know, both has to be done in order to enable an Interupt Service Rountine. But what exactly triggers the Interrupt? For my understanding so far, the peripherie starts an interupt request. No matter if the interrupt at the peripherie was enabled or not, an Interupt Flag gets set. This Interupt Flag triggers the NVIC to start the Interrupt (vector fetching and stacking...) as long as the Interupt Request Channel was activated in the NVIC. Thats why we would end in an Interrupt Request Handler loop as long as we do not clear the Interrupt Flag (pending bit). But why doesn�t it start, if the interrupt is not enabled at the peripherie, though the Interupt Flag is set no matter what?With best regards,Endres  #nvic-peripherie-irq

[Tesla DeLorean]

Posted on March 25, 2015 at 12:49

The peripheral has internal logic to perform it's function, there are registers that reflect the internal states. The interrupt enable on the peripheral side gates the internal status, to the external interrupt line via an AND gate, with the specific interrupt enable for that status.

You can see if the USART peripheral is signalling a TXE or RXNE interrupt, but you can choose if that signal gets reflected to the NVIC. This is usefully in cases like TXE, and you have no data to provide to clear the TXE state. Here you want to disable the TXE interrupt so the processor doesn't keep trying to service it, but the USART still needs to indicate that it's still in this same empty state internally. Most peripheral generate a single interrupt request to the NVIC, but the peripheral may have multiple sources for that interrupt. After the AND Enable arrangement there is an OR of the sources.

[endy]

Posted on March 25, 2015 at 14:09

Hello clive1, 

I´m once again very thankful for your good answers! Thank you very much!I hope I got it right. Just to get sure: The internal status is reflected by the pending bit? So if the pending bit is set AND the interupt is enabled, a signal (command) is send to the NVIC via external Interupt line(?) ?And if IRQ_channel is not enabled for the NVIC, it will be ignored, right?