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Delay in SPI Transfer with STM32H7

Roibert
Associate II

Dear Forum

Im using STM32 H755 ZI in the starter kit.

 

I set the Timer 4 for generate a Interrupt each 1ms.

At begin of INT:

     -I toggle a PIN,

      -and, send a SPI data (8 byte or 16..not important)

What I noted is a delay of almost 10uS beetwen pin toggle and begin of 1st bit TX from

SPI (begin of SPI transmission i means)

Some data:

FCPU=64M coming from internal 64M HSI

SPI1_CLK=4M coming from PER_CLK =64M  (with SPI prescaler=16  -->4M) 

FAPB=64M

Code inside INT Timer:

HAL_GPIO_TogglePin(PF10Test_GPIO_Port, PF10Test_Pin);

HAL_SPI_Transmit(&hspi1, p_Data16b, 1, 100);

__HAL_TIM_CLEAR_FLAG(htim4, TIM_FLAG_UPDATE);

 

Thanks for your help

Roberto

13 REPLIES 13
Roibert
Associate II

Dear Forum.

About my last question, 

I tried to use enable and disable SPI via .SPE, and so, able to reload TSIZE. This make the trasnfer

correct, but i have not 10us as HAL produce, but 2-3 us .

Question are:

-Why so much delay, and, where i find in datasheet ?

-Some explaination to my last question ? (The N2 in last my post). What im missing to read in datasheet ?

Really thanks 

Roberto

Are you still running the core at 64 MHz with no instruction cache and no compiler optimizations?

Why are you so fixated on 10 uSec to set up the SPI transaction?

Thanks Mr David for Reply

I need to generate a SIN at 100KHZ, with a external DAC .  The 100K meand Period=10us.

So, with the HAL delay of 8us circa, im at limit (without consider the SPI transfer time circa 0.5us).

Because i send SPI data in a INT Timer of 10us, for 8us and more, i cant exit to INT...lot of time lost.

Also using DMA (i did not try), i think the delay remain (the DMA will not solve the HAL delay ).

Thanks again

Roberto

 

Roibert
Associate II

Dear Forum

I modify the freq of CPU and SPI, and get to the conclusion that max distance beetwen 2 consecutive transmisson is circa 1uS (distance bettwen 2 H->L transiction of CS) ; in particular:

- delay decrease if Baud rate increase

-delay decrease if CPU freq incresae.

But this decrease reach a minimun, and then stop (not linear).

Question is what is limiting this disrtance ?

Thanks

Roberto