Hello,
I'm a bit confused about how memory addressing and byte alignment works when using two QSPI FLASH memories in dual flash mode.
Accordingly to AN4760 paragraph 2.2.4, in dual flash mode addresses are "splitted" across two banks by sending even addresses to bank 1 and odd to bank 2. That sounds like using address LSB to choose to which bank read/write data to, and address >> 1 as the physical memory address. I can't find anywhere the explanation about how sectors erase works, but I expect that it would work in the same manner by sending the same erase command to both memories with (address >> 1) as the physical address of the sector to erase. This is OK for me, so that the dual bank memory appears as a single memory having sectors of double size and a total memory of doubled size.
Here's where the "strange" behavior comes in: when I attempt to read/write a single byte to the memory (or an odd length bytes array, e.g. 187 bytes long) it seems impossible to handle the read/write operation without reading/writing an extra byte.
I'll try to explain the situation better by giving some example:
- trying to read 1 byte from address 0x00 results in reading 2 bytes from address 0x00 to address 0x01
- trying to read 1 byte from address 0x01 result in reading 2 bytes from address 0x00 to address 0x01
- trying to read 127 bytes from address 0x00 results in reading 128 bytes from address 0x00 to address 0x7F
The same for write operations.
Do you confirm that's the normal behavior of using QSPI in dual flash mode? I would expect to be able to work with 1 byte alignment, not 2 bytes.
Thanks in advance,
Best regards.
