configuring spartan 6

[ramin_alimohammadi]

Posted on June 14, 2015 at 13:04

Hi,

I start designing a board with a SPARTAN-6 fpga (high density:XC6SLX150) need to be configured with STM32F407 (raeding fpga programming data from a SD card and transferring to Spartan). my FPGA can be configured in 2 modes serial and parallel (SelectMap). which take less time to configure? because of large density of my FPGA, using parallel mode seems better solution,but I think, in parallel mode the ports of STM32F407 should be used as GPIO (for both clock and data port) and handling the process take long time (in spite of  for example serial SPI with free clock and data port).  what is your solution? Thanks Tiger

[Tesla DeLorean]

Posted on June 14, 2015 at 16:07

Couldn't you use the FSMC interface? I'd expect the writes in parallel mode to look like access to an external RAM part.

http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf

[Hamid.Wasti]

Posted on June 14, 2015 at 19:09

Theoretically, the SelectMAP in x16 mode can transfer the data in about 10% of the time as the Slave Serial mode (45 milliseconds vs 450 milliseconds), assuming both are running at their maximum speeds. But in real life, the results are going to be different.

In real life, how fast you can program the FPGA will depend on how fast you can actually get the data out of the SD card. My gut feeling is that the SD is going to be slower than the Slave Serial interface. If I were doing this, I would interleave the reading of the SD card and writing of the FPGA in Slave Serial mode. It should be fairly simple to do using ping-pong buffers and DMA. You should be able to get the FPGA programmed in about 110% of the time it takes to read the 33 Mbit from the SD card, or the time it takes to actually write to the FPGA, whichever is longer.

[ramin_alimohammadi]

Posted on June 17, 2015 at 11:46

Dear Clive1,

Tahnks for your post, My main work field is FPGA and I am beginner in ARM. I read FSMC in detail. It seems helpful. but a broblem I occured is that data exits from FSMC with the rising edge of clock and on the other side fpga samples data at the same edge of clock and data may be invalid. I didn't find any control on output clock of FSMC. is there any way to solve this problem? thanks

[ramin_alimohammadi]

Posted on June 17, 2015 at 12:07

thanks for you reply,

could you please tell me more details about using ping-pon buffer? is ping-pon buffer an available resource of stm32 or must be done by softwrae? thanks

[Hamid.Wasti]

Posted on June 17, 2015 at 16:26

> could you please tell me more details about using ping-pon buffer?

Ping-pon

g

(note the ''g'' at the end) buffers is a standard programming algorithm. You have two buffers. One buffer is used for reading data while the other buffer is used to ''consuming'' the previously read data. In the next step, the buffer in which the data was just read is used to consume the data, while the buffer whose data was consumed in the previous step is used to read new data. This way you do not have to move data around and can overlap reading and consuming the data. This is not a beginner level technique. If you are a beginner level programmer, you will likely have to do this sequentially: Write the program to read a block from SD to RAM, write it to the FPGA, read the next block....  Doing it this way, it will take you the sum of the time required to read the data and the time requires to write the data (plus a little more) to program the chip. With overlapping operations, you can get done in the time required for the slower of the two operations, plus a little more. If programming speed is vitally important, you may want to consider getting help from someone in your company who is more experienced in programming and can write the overlapping code.