Comprehension XSPI and XSPIM on H7RS

[beSTMax]

Hello,

I am wondering/unsure about the XSPIM in H/RS MCUs.

I want to connect a quad-SPI NOR flash to an XSPI. Is the XSPIM needed at all?

Let's say the XSPIM is in default configuration, i.e. EN bit in XSPIM_CR is 0.

Does that mean that I can configure the XSPI like I would configure a QUADSPI peripheral?

That is, I would configure GPIOs that the NOR flash is connected to (AF mode, speed, etc.).

Then I would configure the XSPI CR, DCR and so on.

Is that correct? Or do I need to configure the XSPIM (see Figure 194 in RM0477,rev7, there

the XPIM is present).

Thanks!

[KDJEM.1]

Hello @beSTMax and welcome to the community,

The XSPI is the Extended-SPI interface and the XSPIM is XSPI I/O manager.

The STM32H7Rx/7Sx devices embed XSPI I/O manager which is a low-level interface that enables an efficient
XSPI pin assignment with a full I/O matrix (before alternate function map), and multiplex of single/dual/quad/
octal/16-bit SPI interfaces over the same bus.

That means, the STM32H7RS is a product that incorporates the XSPIM, the XSPI interface uses the following lines for Port1:
• XSPIM_P1_NCS1/2 lines for chip select
• XSPIM_P1_CLK line for clock
• XSPIM_P1_NCLK to support 1.8 V hyperbus protocol
• XSPIM_P1_DQS0/1 line for data strobe/write mask signals to/from the memory
• XSPIM_P1_IO[0...15] lines for data
The XSPI interface uses the following lines for Port2:
• XSPIM_P2_NCS1/2 lines for chip select

• XSPIM_P2_CLK line for clock
• XSPIM_P2_NCLK to support 1.8 V hyperbus protocol
• XSPIM_P2_DQS0 line for data strobe/write mask signals to/from the memory
• XSPIM_P2_IO[0...7] lines for data

I think there is no EN bit in XSPIM_CR:

Yes, the XSPI interface can be configured as Quad-SPI for 4-line data transmission. 

Thank you.

Kaouthar

[beSTMax]

---

@KDJEM.1 wrote:

Hello @beSTMax and welcome to the community,

Thank you @KDJEM.1 

---

I think there is no EN bit in XSPIM_CR:

---

 You are absolutely right, there is no such register; I was negligent and meant the MUXEN.

I think what I mean to ask is: The XSPIM has to be enabled (clock on AHB5) for the XSPI signals to be available?

Thanks again!

[KDJEM.1]

Hello @beSTMax,

The XSPI I/O manager (XSPIM) is not a peripheral it is used with the XSPI interface. 

For example if you configure the XSPI1 mode Quad SPI (no multiplexed mode), then generate the code.

 You can see the XSPIM configuration in the generated code

  sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1;
  sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_1;
  if (HAL_XSPIM_Config(&hxspi1, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    Error_Handler();
  }

But, if you asked about XSPIM peripheral clock, you need to set XSPIM clock when using the XSPI interface.  

    __HAL_RCC_XSPIM_CLK_ENABLE();
    __HAL_RCC_XSPI1_CLK_ENABLE();

For more information, I recommend you to look at RM0477 section 7.8.55 RCC AHB5 low-power clock enable register (RCC_AHB5LPENR)

The MUXEN bit is used to enable multiplexed mode.

I hope this answers your request.

Thank you.

Kaouthar