2025-01-20 9:36 AM
I have configured the comparator 2 PB6 on the STM32G071RB Nucleo board. It is configured for rising edge interrupt. As soon as HAL_COMP_Start is called on the COMP you can see the EXTI rising edge interrupt flag immediately go high. (well not immediately, it happens when HAL_COMP_Start is in its startup wait loop so presumably as soon as the COMP peripheral physically starts up.) This happens even if I change it to falling edge but I guess that should be expected. but certainly not reliably both!
It seems that this is how the MCU works as I can't find any obvious mistakes in the LL or HAL driver startup function. I have seen several posts to this effect over the last 4-5 years with 1 to 2 replies but no solution. I think the reference manual needs to mention that this will happen as it seems to be an MCU behavior. Is it only the G0?
The COMP output also triggers. But the input does not move. My guess is that when COMP is activated the initial value of the negative input is initializing and low to COMP and causes a trigger. But I don't know as I can't tell any internal MCU values. This happens even if I use DAC as the negative input. I guess its kind of expected and maybe the interrupt should not be on before the COMP? But that's how the IDE does it.
Note: this is not a real trigger based on real circuit voltage. Please test this for yourself. I have changed from my custom board to the demo board to avoid the questions about the hardware.
Below you can see the INP in green. Negative is 3/4 refint voltage. You can see a slight bump in INP that I assume is due to GND shift from the COMP drawing a bit more power? Anyway, not enough to properly trigger. Yellow is the COMP output.
This happens only at start but no false triggers afterward.
Solved! Go to Solution.
2026-01-21 1:21 AM - edited 2026-01-21 1:26 AM
This explains it.
ADC sampling means, that a sampling capacitor charged to some unspecified voltage is connected to the signal input.
Depending on the signal source's impedance, this generates a voltage spike, and the comparator "sees" it.
Transients during COMP startup may make this worse.
JW
2026-01-21 2:42 AM
I agree. However, the previously sampled channel is an exact replica circuit. So in theory it should have been charged to the same voltage. But i guess there's more to it than that.
2026-01-21 4:58 AM
> So in theory it should have been charged to the same voltage.
ST does not specify this nor does ST publish the exact architecture from which this could be inferred.
I've experimented and found that for example on a 'F4, if you take repeated conversions on a single floating pin, even if you ground it briefly i.e. you start from 0V, the conversion leaves the sampling capacitor at a nonzero voltage and the pin will eventually drift to cca 0.7V (while VREF+ is around 3V).
JW
2026-01-22 9:13 AM
I also made provisions to sample a grounded pin prior to this sample. But I thought what could be better than sampling the same voltage. Sometimes things just work until they don't.