Clock recovery system CRS

[pferd]

Hello,

I have problem with CRS (Clock recovery system) in STM32F091xx. I use HSI48 and I want to generate synchronization with LSE (32.768 kHz).

How to set FELIM in CFGR register and TRIM in CR register ?

Thank your for help.

[TDK · Accepted solution]

Set RELOAD and FELIM fields accordingly in the CRS_CFGR register.

RELOAD = (fTARGET / fSYNC) - 1

FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2

For you, fTARGET=48MHz, fSYNC=32kHz, and STEP=0.14%.

TRIM is adjusted automatically. You don't set it manually.

[pferd]

Thank you for help !​

[BChan.4]

It is best to keep in mind that the intended fSYNC target is around 1kHz based on the USB SOF. This yields a FELIM of 34 which CubeMX defaults to. Using fSYNC=32768 causes FELIM to be 2 which is a very small margin and causes CRS to auto trim much more frequently than intended. I am using LSE/32 for fSYNC=1024 and FELIM of 33 based on the equations above.