I'm working on a STM32G473RCT6 CPU with 256K Flash in dualbank mode.
looking for information on addressing the 2 banks of flash in CPUs with less than 512K I came across this post which clarifies the issue:
https://community.st.com/t5/stm32-mcus-products/flash-layout-of-stm32g4xx-cat-3-with-less-than-512-kbyte-missing/td-p/287276
but the following facts do not convince me:
-stm32cubeProgrammer correctly detects my CPU and in the sector deletion screen it offers me the selection of banks from 0 to 127 with addressing from 0x08000000 to 0x08040000
-I wrote a firmware resident between 0x08000000 and 0x080054b4 that performs sector-by-sector erase/write/reread operations starting from 0x0800C000 up to 0x08080000 and I saw that in reality there are 512K of working flashes and I also had no problems erasing the pages (2K, with FLASH_TYPEERASE_PAGES) 0-127 of bank 1, the same one from which the code was executed and to write (FLASH_TYPEPROGRAM_DOUBLEWORD) in the locations 0x0800C000-0x08020000 and 0x08040000-0x08060000 which should belong to bank 1.
everything happened calmly while interrupts of the system timer and of the uart with which I printed the information via serial were active
I also thought that the instruction cache could save me from simultaneously reading and writing on flash, but even by disabling it it continues to work normally
I would like to understand how all this is possible when the hardware manual expressly says the opposite.
