Clarification on Debug Register Configuration in STM32H755

[wukong]

Hi,

I'm working with the NUCLEO-H755ZI-Q, which features dual cores (Cortex-M4 & Cortex-M7). I’m trying to understand whether these two cores have separate debug registers, such as DHCSR (Debug Halting Control and Status Register).

I have reviewed RM0399 and the Armv7-M Architecture Reference Manual, but I couldn't find a definitive answer. To investigate further, I attempted to access DHCSR (0xE000EDF0) on AP0 and AP3 using STM32CubeProgrammer, and I observed that both cores displayed the same value. However, when running a project in STM32CubeIDE, where I separately access DHCSR on M4 and M7, I see different values for each core.

This discrepancy has left me confused about the debug register configuration on STM32H755. Do Cortex-M4 and Cortex-M7 maintain independent debug registers, or are they shared?

Any insights or official documentation references would be greatly appreciated!

[TDK]

Each core has its own debug registers. The DHCSR register and other debug registers are part of the Cortex core.

[wukong]

Thank you for your help! Is there any manual or example that supports this?

[wukong]

Assuming that each core maintains its own set of debug registers, how do the M4 and M7 cores get different values ​​when accessing the same physical address 0xE000EDF0?