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Can VREF+ be zero?

Senior III

In STM32F437 data sheet it says VDDA - VREF+ < 1.2 V.

Is that a "global" limitation or just a working limitation?

If VDDA is 3.3V and VREF+ is 0V, can that harm the chip, or is it just that the conversions don't work right?


Could you please give us the device number for the reference voltage generator, just for checking 

Device number? The board is or own design and uses STM32F437ZGT6.

I don't know which regulator is used. It's not in the official schema yet. But another proto round is coming.

And like I tried to express, the VREF+ doesn't have a dedicated voltage generator. Instead tha same voltage goes to some off-board devices, whose output we are measuring with the ADCs.

Is it possible just to know about the two cases: REF+ grounded and REF+ left open?

That knowledge might change the implementation.

I guess I need to add the second "like" textually.

BTW, we use 7 ADC channels. If that has any meaning here.

(At least it rules out any possible tricks with the internal reference voltage.)

Senior III

OK. Our client got the answer from STM in another way.

"I confirm VREF+ could be grounded when ADC and DAC are not active but you need to make sure that the VREF is stabilized before to start the ADC conversion. About VDDA should be connected as soon you have VDDa pin on the MCU because it is the power supply for all the analogue parts of the MCU - Reset blocks, RCs and PLL. "