CAN problems STM32F427IIT6

[jvankuilenburg]

Posted on October 20, 2014 at 11:51

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Dear,

We have a new pcb with a STM32F427IIT6 processor

I have 2 strange problems with the CANbus:

A: CAN2 is not working correctly. I initialize only the CAN2, not CAN1. When I send a message, the CAN2 put a undefined message on the bus. The bittiming is okay. But the data is undefined. The problem is

that the

sTxMailBo

x

is

not updated to the value that

is

writ

ten

into the registers. The sTxMailBox

is

not pending,

all

the TMEx bits are high. The other status bits are okay and changes correctly when I send a message. The problem is solved when I activate the clock of CAN1, only the clock, not the init of CAN1. Whats the relation between the CAN1 clock and the CAN2?

B:

Both CANs give sometimes a form-error on the bus. The send messages are put on the bus, but the bus is instable. It gives a lot of form-errors. The bittiming is okay, I measured wit

h

the scope. The system clock runs with 180Mhz and the APB1 with 45 Mhz. When I reduce the system clock to 168 Mhz and the APB1 to 42 Mhz (and the can-bittiming reg.), the bus is okay. There are no form-errors. Its look like that the CANblock can not runs with 45Mhz. Why not?

Jan.

#can

[waclawek.jan]

Posted on October 20, 2014 at 12:14

>

Whats the relation between the CAN1 clock and the CAN2?

RM0090 rev.7, p.1060:

Dual CAN •CAN1: Master bxCAN for managing the communication between a Slave bxCAN and the 512-byte SRAM memory •CAN2: Slave bxCAN, with no direct access to the SRAM memory.

[jvankuilenburg]

Posted on October 21, 2014 at 07:13

Thanks,

the dual can combination is new for me, (also the ST micro). It was for me not clear from the manual,

little bit summarily description.

[Tesla DeLorean]

Posted on October 21, 2014 at 10:14

CAN2 requires that CAN1 is clocked.

You might want to confirm the internal PLL clock is sufficiently stable. You can export a fractional version of the internal system clocks via the MCO1 pin (PA8). The 180 MHz setting requires additional RCC options (over drive). I'm not sure what the maximal speed is for the CAN peripheral, the APB clock can of course be decimated more than default setting.