big gap between CS and SPI transmit

[HDaji.1]

  // CS pin go low to select
  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET);
 
  HAL_SPI_Transmit(&hspi1, (uint8_t *)spi_buf, 3, 10);
 
  // CS pin go high to release
  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);

I use the above code to communicate with a device through SPI.

The green line D10 in the above picture is chip select (CS) signal. The gap between CS-enable and clock start is about 13 us, so is that between clock stop and CS-disable. It's too much waste of time. Anyone knows how to reduce it?

[Danish1]

1. The HAL hardware-abstraction-layer adds many instructions - checking that clocks are enabled, that function-call arguments are credible, locking access to peripherals so no other thread can interfere etc, before descending to LL low-level function calls. If you write registers directly (see the reference manual, and look at the source-code for the HAL function calls), things will be many times faster.
2. You do not say how fast your processor is running. Increasing the system clock will increase the speed of HAL execution
3. You do not say if you are compiling in debug or release mode. Debug is great for single-stepping, but it needs many more processor-instructions per line of code.

Hope this helps,

Danish

[HDaji.1]

1. Do you mean this function HAL_StatusTypeDef HAL_SPI_Transmit? I will study it. I wonder if I use DMA, will make it faster?
2. I am using stm32 nucleo f411re discovery board. Its HSE_VALUE is 25000000U.
3. I changed debug to release mode. The timing did not change.