Hello
This is my first time soldering a MCU on a custom PCB.
As you know, STM32f767 is a very complicated chip and requires Vdd and Vss on many pins. Datasheet also states that capacitors are mandatory on each Vdd or Vref+. However Vref and Vdd (marked on figure) are neighbors and I was wondering if I can use one capacitor for both of them.
Could you also tell me if this is a proper way of placing capacitors ? Max distance from Vdd line and cap is 8mm.
As you can see, there is only one track and its obviously Vdd line.
Of course I am not done with placing all caps and tracking Vdds to pins. I first need to know if this kind of principle is going to work
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You will find many different opinions on how to place decoupling caps. In general, the closer the better.
Using the same cap for VREF+/VDDA seems fine, unless you want to really optimize ADC noise performance.
Take a look at ST's own layouts to see how they do things. Here's an example from a Nucleo board so you can see how far the decoupling caps are. Some boards out there have decoupling caps way farther away than this--maybe 1cm or so, and yet the board works fine. It really depends how you're using things.
Your images show up.
You will find many different opinions on how to place decoupling caps. In general, the closer the better.
Using the same cap for VREF+/VDDA seems fine, unless you want to really optimize ADC noise performance.
Take a look at ST's own layouts to see how they do things. Here's an example from a Nucleo board so you can see how far the decoupling caps are. Some boards out there have decoupling caps way farther away than this--maybe 1cm or so, and yet the board works fine. It really depends how you're using things.
