it seems that a write to AXI SRAM very shortly before a system reset (via AIRCR) gets lost. I wrote a very short block of code that simply reads a word from 0x24000000, increments it, writes it back, and resets the processor. I can see that the value is not changing. Using a debug tool, I can see that, if I manually modify the contents of memory, the register used for the increment changes accordingly. Also, if I use the debug tool to display that memory location after the code should have written it, it shows the new value. However, if I let the code write back the new value, then reset the processor, the memory reverts to its old value after the reset (as shown both by reading the memory directly or by displaying the register).
I saw this note in the reference manual: “When a half word is written to an internal SRAM and a reset occurs, this half word is not really written to the SRAM after reset. This due to the ECC behavior.�? However, this does not apply: I am doing full-word-size reads and writes. It also can’t be a cache issue because I have the caches turned off. I have set PWR_CR3 appropriately (without which SRAM is apparently read-only), and I have set AXI_TARG7_FN_MOD.READ_ISS_OVERRIDE=1 due to the erratum. I have the necessary DSB before writing to AIRCR. I also tried introducing an ISB as well. I also tried (as recommended in the Cortex-M programming guide to barrier instructions, AN321) adding a dummy read from the AXI SRAM after the write, including with a DSB+ISB both before and after the dummy read. All to no avail.
Everything seems to work just fine during normal operation; it’s only after reset that this problem shows up. This problem doesn’t seem to happen if I use the DTCM or the AHB SRAM, only the AXI SRAM.
Any ideas?
