โ2019-12-31 02:38 PM
Hi, Im searching way to avarage two unsigned 32 integers.
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Is there any hardware help in doing this with stm?
Solved! Go to Solution.
โ2020-01-01 08:39 AM
unsigned 32-bit, the assembler would allow for a two register add with carry output, then rotate right to recover the overflow carry, and then decide if you need the low-order bit dropping into the carry should round up, or not, basically an ADC with zero immediate.
So 2 or 3 assembler instructions, all fast ones
โ2019-12-31 05:18 PM
Smells like a homework assignment. Division by powers of 2 with unsigned math is super easy. โ
โ2020-01-01 12:18 AM
Man ... oh man =) Im not asking for software implementation but is there a hardware acceleration =) in stm32.
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IThink I read that some stm's support hardware ADC avaraging (addind next measurments and bit schifting).
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Its hobby, too old for homework :)โ
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โIm interested in stmf103 f303 h750 - playing with this micros :)
โ2020-01-01 12:26 AM
It already show that your question is not specific enough to get the anwer you look for.
Averaging 2 numbers by hardware... the core is not?
Well, at least look for FMAC CORDIC DFSDM peripiherals on the web to look for non core application specific accelerators.
โ2020-01-01 01:09 AM
Well Yes, question was not specyfic enough :) I ment without core.โ
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Thanks :)โ
โ2020-01-01 04:54 AM
The ADC averaging module is hardwired to average ADC values.
DMA2D can average 8 bit values, like blending two bitmaps.
DFSDM can do 16 bit averages, much like the one in the ADC, but it can take input data from DMA.
Nothing I know of can do 32 bit averages outside the CPU core.
โ2020-01-01 06:13 AM
So I implemented it in software.
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But is it super easy? If it would be super easy there wouldnt be us patents solving this problem :) I think. โ
โ2020-01-01 06:54 AM
Entertaining a cat with the shiny dot of a laser pointer must be a quite complicated task then, because there are no less than 5 patents covering it.
โ2020-01-01 07:24 AM
Cast them as floats and use the fpu?
That's some hardware.โ
โ2020-01-01 08:39 AM
unsigned 32-bit, the assembler would allow for a two register add with carry output, then rotate right to recover the overflow carry, and then decide if you need the low-order bit dropping into the carry should round up, or not, basically an ADC with zero immediate.
So 2 or 3 assembler instructions, all fast ones