2025-01-27 05:51 AM - last edited on 2025-01-27 05:52 AM by Andrew Neil
Hi ,
We are working on configuring an ISSI Octal Flash memory in DTR mode on the STM32U5 platform and would like your assistance.
We successfully executed the example provided for Macronix in document an5050 example (II. Octo-SPI FLASH in Regular-command protocol example ) flash to enable DTR mode and were able to perform both read and write operations. However, while trying to replicate the same for the ISSI chip that we have interfaced with STM32U5A9J-DK , we modified the instructions, dummy cycles, and address configurations based on the ISSI datasheet.
Here is the sequence we followed to configure the ISSI flash for DTR mode:
Configure 4-byte address mode:
We wrote to the volatile configuration register at address 0x05 to enable 4-byte addressing.
Enable Octal DTR mode:
We configured the flash for Octal DDR mode by writing the value 0xE7 to the volatile configuration register at address 0x00.
Verify DTR mode:
We read back the volatile configuration register at address 0x00 in DTR mode, and the value was correctly returned as 0xE7.
Your guidance and insights will be highly valuable for us. Please let us know if you need any additional information regarding our setup or configurations.
Thank you in advance for your support!