APMemory APS12808 OSPI memory connection to STM32H723ZGT6

[Maxim357]

Hello,

I am writing to seek advice on connecting an APMemory APS12808 OSPI memory to the STM32H723ZGT6 microcontroller.

Initially, I attempted to adapt the code from this thread ( https://community.st.com/t5/stm32-mcus-products/stm32h7-octospi-mode-hyperbus-hyperram-access-and-delay-block/td-p/143237/page/2 )  from @Alex - APMemory  to the STM32H723ZGT6. You can find the result in the attached file `main_1.c`. With this configuration, read and write operations do work, but I am encountering issues with data mismatches/corruption.

Subsequently, I tried to enable the Memory Mapped mode based on Application Note AN5050. This is where significant problems began I cannot get this mode to activate. The relevant code is in the attached file `main_2.c`.

My specific questions are:

1. Is there a known working example for enabling the Memory Mapped mode for this type of memory?

2. Why does AN5050 not cover the MR (Mode Register) configuration and memory initialization sequence?

3. Is there any functional difference in which OCTOSPI interface (OCTOSPI1 or OCTOSPI2) is used to connect the memory?

4. Is it acceptable to leave the memory's RESET pin unconnected (floating) if it is not being used?

5. Can I use pins with different Alternate Function (AF) numbers within the same OCTOSPI connection (e.g., for data lines), or must they all belong to the same predefined AF group?

6. There is a dedicated driver available here: ( https://github.com/STMicroelectronics/stm32-aps6408 ). How current and reliable is this driver? Are there any usage examples available?

7. In this thread ( https://community.st.com/t5/stm32-mcus-products/unable-to-read-reset-values-of-the-stm32h730vb-octospim/td-p/212094 ), I read about the OCTOSPIM clock being disabled by default. Is this issue still relevant for the STM32H7 series, and are any specific actions required to ensure proper memory operation?

8. On one of my PCB revisions, the memory's B1 pin is accidentally tied to ground. Is this configuration acceptable, or will it prevent the memory from functioning correctly?

Thank you for your assistance.

Best regards, Max

[Alex - APMemory]

Hi, 

The regW_MR0[0] is 0x24, yet regR_MR0[0] is 0x88.

Clearly the XSPI bus timing has some issues.

Have a logic analyzer to see the exact transaction waveform on all XSPI bus,

this will give you the definite answer on the next step.

regards

Alex

[Maxim357]

Good afternoon,

I have successfully established communication with the memory and performed a basic write-read test operation.

However, the Mode Register (MR) values still do not fully match the expected values, even though operations seem to be proceeding.

Could you please advise on the correct way to determine the proper MR values?

Furthermore, I purchased a Wio Lite AI board and realized there might be issues with my own board's design.

I have two reference designs: one from the MB1242 and another from the Wio Lite AI.

 

 

 

In both of these designs, the RESET pin is connected to VDD.

What is the purpose of this?

Is it necessary to add a series resistor and a capacitor to ground on the CLK line?

Doesn't this overcomplicate the design?

Should the Chip Enable (CE) pin be pulled up to the power supply via a resistor?

Is a 10μF capacitor in the power supply circuit a good idea?

Why are pins A2 and A5 connected to the power supply circuit in the MB1242 design?

Maxim