AN4661 interface signal layout guidelines for high speed SDMMC operation states "keep the same number of via between data signals". Am I interpreting this correctly?

[RMora.4]

I am interpreting this to mean that each data signal (including CMD line) should all contain equal number of vias. For example if line D0 is routed to MCU and this trace requires 2 vias on its path to the MCU then all other data signals should also contain 2 vias on their path to MCU.

Is this the correct interpretation?

[Tesla DeLorean · Accepted solution]

I believe so.

You want to have roughly equivalent circuit paths (lengths, detours) for all the signals so as not to unnecessarily skew them with respect to each other.

I might also consider 27R or 33R series resistors on short "high-speed" traces of this nature to stop reflections and standing waves/ringing, and perhaps back-off on the slew-rate (SPEEDR) so as not to dump too much energy into the lines.

The Dx and CMD pins should have 47K, or similar magnitude, at the socket.

Some of the designs using eMMC might be instructive for those clocking >50 MHz

[RMora.4]

Thank you for the guidance.