Address mapping of 1GBit of continuous memory (Parallel NOR Flash M29EW) - FSMC/FMC

[Zaher]

Hello Folks!

So far, I've been able to utilize the FSMC/FMC peripheral in many different scenarios, including interfacing LCDs in 8080 mode, legacy ASICs, SDRAMs, etc. I'm now working on a project that involves M29EW Parallel NOR Flash (1GB single-die TSOP) and I was wondering if the FMC (STMF429) can address 1 GB of continuous memory space. As far as I know, BANK 1 of the FMC that is dedicated for the NOR-type of memory is divided across 4 sub banks with an individual chip-select (NE) for each bank. With that being said, if I have configured the FMC for 26 address bits on a given NE, would it be possible then to address a 1-GBit (128 MBytes) of continuous memory space?

Thanks,

Zaher

[Tesla DeLorean]

M29EW_CE = FSMC_NE1 & FSMC_NE2

M29EW_A25 = FSMC_NE1

M29EW_A[0..24] = FSMC_A[0..24] - ARM_A[1..25]

M29EW_D[0..15] = FSMC_D[0..15]

Plus whatever you need to do with read, write and byte lanes, etc

[Zaher]

Thank you very much for the detailed and very helpful input. The part # is: JS28F00AM29EWLA. I have attached the datasheet for reference at will.

Yes, I was thinking about doing some experimentation on the STM32F429 board level by monitoring the state of the FMC pins during bus transactions. However, I do not have the flash connected to the board at the moment, so I'm not sure if I can do the job right now without connecting an actual memory to the FMC peripheral. I guess some timing and signal feedback rules apply here. Not sure if that can work out without an actual memory device.

Thank you again for your excellent support!

[Zaher]

By the way, since NE2 has to be enabled in the CubeMX configurations, I think I must have two separate setup and access functions for each handle. This is another limitation, but I guess it's not difficult to write some functions to get things automated for read/write access on both banks in the 128MB space.

I'm almost done on the PCB. I should have a prototype with an exposed header so I can change the wiring between the STM32F429 and the M29EWL at will.

[Tesla DeLorean]

Like I said earlier, the decode banks are 64MB wide, you need to AND NE1 with NE2

[waclawek.jan]

This could've been quickly tried also with a Nucleo-type board with a small SRAM such as 6264/62256 or a small 29Fxxx FLASH (or, for that matter, a 27xx EPROM or 28xx EEPROM) wired up to the highermost addresses.

JW

[Zaher]

Well, I wanted to give it a try on an actual 1 Gbit M29EWL so I have designed and ordered the PCB for this purpose. I made it with a pin header so I can exchange signals at will between this prototype PCB and the STM32F4 board. I will report my testing over here once done!

Thank you guys!

[Zaher]

Again, access to the second 64 MB (sub-bank 2) fires a Hard Fault interrupt if NE2 was not enabled initially. This is also mentioned in the RM of the device. With that being said, there will be a separate hnor handle for configuring/accessing the memory for each individual sub-bank. I guess I will have to write a function in such a way that switches between handles/sub-banks accordingly. Please correct me if I was wrong or if you think there's a better way to do it.

[waclawek.jan]

> access to the second 64 MB (sub-bank 2) fires a Hard Fault interrupt if NE2 was not enabled initially

Simply enable both sub-banks and with the "address reconstruction" and merging the chipselects (NEx) you should be able to access a continuous 128MB space.

JW

[HTung]

Hi guys,

Thank you very much for your information, could you please tell me more detail about "the "address reconstruction" and merging the chip selects (NEx)" as you mentioned?