ADC Sampling rate calculation?

[sv2agw]

Posted on May 04, 2015 at 18:49

Hi

I am using discovery board with stm32f429. I configured well the ADC for DMA and works fine but I don't know what is the sampling rate. Anyone can explain how to calculate it? The clock is at 90Mhz the prescaler is

ADC_CLOCKPRESCALER_PCLK_DIV8

samplingTime is

DC_SAMPLETIME_84CYCLES

My calculations says that sampling rate is 46875. Is that right?

Thank you in advance for any help Georges

[raptorhal2]

Posted on May 04, 2015 at 19:17

The sample cycles total is the programmed sample cycles plus the conversion cycles of 12, 8 or 6 depending on the conversion resolution. The DC_sample cycles is the number of cycles the sample and hold capacitor is being charged before the value is held for conversion. So the sample frequency is probably (90 MHz/8)/(84+12 cycles) = 117 KHz if you are converting continuously.

Cheers, Hal

[sv2agw]

Posted on May 05, 2015 at 08:05

 I made wrong calculations.

Now something else I read ,somewhere, that the ADC clock should be between 600Khz-30Mhz. This is the ABP2/Prescaler? In my case 90/8=11,25Mhz or the 117Khz sampling rate. Thank you Georges

[raptorhal2]

Posted on May 05, 2015 at 15:10

ADC clock frequency is defined in the STM32F427/STM32F429 Data Sheet, section 6.3.21, and lower/upper limits are 600KHz/36MHz. Other data sheet ADC performance numbers use the typical 30 MHz value. It is the frequency output of the prescalar.

One ADC clock is one sample and hold or one conversion cycle. In your example, 96 cycles are needed for one value. So your sampling frequency should be based on 96 cycles. Cheers, Hal

[Tesla DeLorean]

Posted on May 05, 2015 at 16:56

Or use a timer to pace the conversion at a desired rate rather than play games with the APB, prescaler, and sample time.

[sv2agw]

Posted on May 12, 2015 at 08:14

Hi

thank you. Finally I set a timer to get the proper samplerate and works almost fine. Georges