2020-05-14 03:58 AM
Hello, I am developing a circuit using STM32L4R9AI, VDD = 1.8v, VDDA&VREF+ = 3.13v, according to ST hardware design manual (I attached) for a better power filtration there should be bead between VDD and VDDA, will that create a problem given the voltages I used?
As I know bead equivalent circuit is inductor in series with small resistor so I am shorting the 2 voltage this way?
the bead I will use is BLM15BX601SN1D
Solved! Go to Solution.
2020-05-14 06:04 AM
> will that create a problem given the voltages I used?
Yes. In the case that VDD != VDDA, you don't want a ferrite bead between them. The app note suggests a ferrite bead in the case when VDD=VDDA, which is a requirement for the majority of STM32 chips, but not this family.
2020-05-14 06:04 AM
> will that create a problem given the voltages I used?
Yes. In the case that VDD != VDDA, you don't want a ferrite bead between them. The app note suggests a ferrite bead in the case when VDD=VDDA, which is a requirement for the majority of STM32 chips, but not this family.