ADC glitches

matej23 · ‎2011-09-24

Posted on September 24, 2011 at 18:39

I have 1kohm potentiometer connected on pin PC4. On the sam pin oscilloscope is connected . Everything is correctly grounded and supplyed. On the scope (attached picture) I see 100mV glitches with a frequency of ADC conversion time (when I change sampling time the frequency changes also). Does anyone have the same problem? Is there a mistake in my code or with my board or is that ''normal''?

I hope that someone can offer a solution or an explanation.

MA

Code:

RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOC, ENABLE);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;

GPIO_Init(GPIOC, &GPIO_InitStructure);

ADC_DeInit(ADC1);

ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;

ADC_InitStructure.ADC_ScanConvMode = DISABLE;

ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;

ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;

ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;

ADC_InitStructure.ADC_NbrOfChannel = 1;

ADC_Init(ADC1, &ADC_InitStructure);

ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5 );

ADC_Cmd(ADC1, ENABLE);

ADC_ResetCalibration(ADC1);

while(ADC_GetResetCalibrationStatus(ADC1));

ADC_StartCalibration(ADC1);

while(ADC_GetCalibrationStatus(ADC1));

ADC_SoftwareStartConvCmd(ADC1, ENABLE);

raptorhal2 · ‎2011-09-24

Posted on September 25, 2011 at 01:12

It's elementary my dear Watson. Each ADC channel has an input impedance of 1K ohms feeding a sample and hold capacitor. At conversion time, the S&H capacitor is draining current from your signal source until it gets charged up, and you see this as a voltage spike. To get a precise conversion, your input signal needs to come from a low impedance source such as an operational amplifier, or an RC network. The op amp allows accurate high speed conversion, the RC network may need a long sample time to charge up the S&H capacitor.

Read AN2834 How to get the best ADC accuracy in STM32F10xxx devices for further details.

Cheers, Hal

matej23 · ‎2011-09-25

Posted on September 25, 2011 at 09:58

I was aware of input impedance before I posted here and tested with an opa as a voltage follower. I used OPA350 and LM358 and the glitches were still present.

raptorhal2 · ‎2011-09-25

Posted on September 25, 2011 at 20:25

The OPA350 is an excellent choice and should work well, especially if set up per the TI datasheet to optimize the output slew rate. I am not familiar with the LM358.

If I am reading the time scale correctly, the glitch is approximately 3 usec. If you are running the ADC clock at 14 MHz, the programmed 55 sampling cycles is approximately 4 usec., so the sampling capacitor is fully charged before the ADC converts the signal. So you should be getting accurate conversions.

My conclusion: the glitches are a normal result of signal impedance. If the glitch is not present in the converted value, press on. If present, increase the sampling cycles.

Cheers, Hal

matej23 · ‎2011-09-25

Posted on September 26, 2011 at 07:18

The ADC clk is 12MHz (datasheet). With sampling time of 55.5 cycles +12.5 cycles the result is 5.67us. This is exactly the same as the time between two glitches. The problem is that the converted value is floating sometimes for more than 20 units. With change of sampling time the time between two glitches is changed and can be calculate with upper formula for an example of 55.5 cycles.

raptorhal2 · ‎2011-09-26

Posted on September 27, 2011 at 01:57

I did misread the time scale. The glitch has settled down well before conversion.

The ADC clk is 12MHz (datasheet).

The ADC clock frequency in the datasheet is the maximum recommended. The actual clock frequency is (or should be) set up in your code as a fraction of PCLK2.

The VL board circuitry follows ST guidelines for VDDA power (uses an inductive/capacitive noise filter) and capacitive filtering for VDD1 to VDD4. The 20 counts of noise is more than the 5 mv noise seen on the oscilliscope, but it may be difficult to find the source. If you can't find the source, and the 20 counts are not acceptable, oversample and filter the converted value.

Cheers, Hal

dennisvantienhoven · ‎2011-09-27

Posted on September 27, 2011 at 14:16

@baird.hal.001

The VL board circuitry follows ST guidelines for VDDA power (uses an inductive/capacitive noise filter) and capacitive filtering for VDD1 to VDD4

In which document can I find this ST guidelines for the VL board?

I want to know how this is done.

Greets,

Dennis.