Posted on January 15, 2018 at 12:43 I am working with ST32F091. I am trying to trigger ADC with TRGO of TIM15. I am able to drive my TIM15 independently (checked with interrupt) and ADC also independently (checked with interrupt), but I am unable to trigger ADC from TRGO of TIM15. this is my source. can anyone advice me what I am missing?
void Timer15_Init()
{
/*Configure the TIM17 IRQ priority */
HAL_NVIC_SetPriority(TIM15_IRQn, 5 ,0); //set at 5 priority
/* Enable the TIM17 global Interrupt */
HAL_NVIC_EnableIRQ(TIM15_IRQn);
//TIM15 is by defaault an upcounter!
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); //enable the clock for TIM15
//TIMx_ARR, no one shot mode,any of the events generate an update interrupt,
//update UEV enabled - buffered registers are loaded with their preload values.
TIM15->CR1 |= (TIM_AUTORELOAD_PRELOAD_ENABLE | TIM_OPMODE_REPETITIVE | (1<<2) | (0<<1));
//compare Pulse - the trigger output send a positive pulse when the CC1F flag is to be set
//as soon as a capture or a compare match occurred.(TRGO)
TIM15->CR2 |= TIM_TRGO_OC1REF;// | TIM_TRGO_OC1;
TIM15->PSC = 12000;
TIM15->SMCR; // no change in SMCR, using as master mode!
TIM15->DIER |= (1<<1); //enable Capture/Compare 2 interrupt enable OC1F
TIM15->ARR = 3000 - 1; //12MHz is CK_INT = 83nS for 1 cnt approx.
TIM15->CCR1 = 3000 - 1;
TIM15->CCMR1 |= TIM_OCMODE_TOGGLE;//TIM_OCMODE_ACTIVE;
TIM15->CCER |= TIM_CCER_CC1E; //capture/compare 1 output enable
TIM15->BDTR |= TIM_BDTR_MOE; //(1 << 15); //MOE Main Output Enable
TIM15->CR1 |= TIM_CCx_ENABLE; //enable the counter which in turn enables the internal clk!
TIM15->SR = 0; //rc_w0!
}
and ADC code...
void MyADCInit()
{
/*Configure the TIM17 IRQ priority */
HAL_NVIC_SetPriority(ADC1_COMP_IRQn, 4 ,0); //set at 5 priority
/* Enable the TIM17 global Interrupt */
HAL_NVIC_EnableIRQ(ADC1_COMP_IRQn);
//Stop and disable ADC with all the possible affecting bits...
ADC1->CR &= ~(ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN);
EnableADCClock();
// We need ADC->CFGR1 for
// 16DISCEN - Discontinuous Mode - 0 Disable, 1 Enable
// 15AUTOFF - Auto Off Mode - 0 Disable, 1 Enable
// 14WAIT - Wait Mode - 0 Disable, 1 Enable
// 13CONT - continuous Mode - 0 Disable, 1 Enable
// 12OVRMOD - Overrun mgmt mode - 0 Protects old data from overwritting, 1 overwrites
// 11:10EXTEN[1:0] 00 - disable hardware trigger
// 8:6EXTSEL[2:0] 000 - External trigger source
// 5ALIGN - Data Alignment - 0 Right
// 4:3 RES[1:0] - 00 12 bit resolution
//2SCANDIP - 0 Upward scan
// 1DMACFG - 0 DMA one shot mode
// 0DMAEN - 0 DMA Disabled
//TRG4 for TIM15 external trigger enable
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_DISCEN;
ADC1->CFGR2 &=(~ ADC_CFGR2_CKMODE); //select ADCCLK(Asynchronous clock mode)
//ADC1->SMPR &=(~ ADC_SMPR_SMP_0);
ADC1->SMPR |= ADC_SMPR_SMP_0; //max sample time, invert AND for min
ADC1->IER |= ADC_IER_EOCIE; //end of conversion interrupt enable
Calibrate();
ADC_Enable();
}
