ADC Conversion time and Sampling time

[luke514]

I have an stm32f407g.

In the reference manual (in the ADC section) I found several terms I am afraid I have confused between them.

I would like to explain my reasoning with an example and get your feedback if I said something wrong.

-------------------------------------------------EXAMPLE (points are in order!)---------------------------------------------------------------

Suppose I need to sample a signal and I need a Tsample = 166.6 us

I need to tell the ADC to sample with that Tsample, however, I need to convert it to cycles:

With some approximation I find 480 cycles --> Tsample = 192us (a little different from 166us but it's okay)

EDIT: I have to take into account that the datasheet says that Tconv = Tsample + 12 cycles

          so actually ADC takes Tconv = 480 + 12 cycles = 492 cycles = 196.8us .. not 192us 

                             

1a) Are these calculations correct?

How long does it take the ADC to convert each sample?

It depends on the resolution, right?

If I use 12 bits, the ADC will need 12 cycles + 3 cycles = 15 cycles ... which converted to seconds are:

15 * 1 cycle duration = 15 * 1/(PCLK/Perscaler) = 15 * 1/(10MHz/4) = 5us.

2a) Are these calculations correct?

2b) Does this mean that every Tsample = 192us the ADC read a sample and takes 5us to convert it?

----------------------------------------------------------------------------------------------------------------------------------------------------------

I hope I have been clear.

[AScha.3]

steht wunderbar im rm :

so with this example settings adc converts in 0,5us .

this kind of adc are capacitive SAR converters , see:

https://www.analog.com/en/technical-articles/successive-approximation-registers-sar-and-flash-adcs.html

https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf

so: sampling time is first part of conversion, where the input cap C is connected with the input pin and charges to the voltage at this pin. then comes the fixed 12 cycles ...together this is the total conversion time. ok ?

first question is : what conversion rate is needed?

- at seldom time 1 x -> start adc by software

- at very high rate : set adc to continuous mode and adjust speed by setting its clock and sampling time (here 2MHz rate)

- at desired medium frequency , ie 10kHz rate : set a timer to generate this 10k and start adc by trigger from this timer.

[luke514]

I have edited my question with your clarification regarding Tconv.

Thanks!

[Tinnagit]

there are many stuff in ADC Sampling time but there are 3 necessary stuff.
1. ADC Clock is divider from APB-CLK which it has a limit and less than APB Clock.
2. Sampling Cycle is how long time does it take to use for sampling.
3. Conversion Time is how long time does it take for convert from analog to digital which it depend on ADC resolution.

for a single channel you can calculate how many cycle to use by SamplingCycle+ConversionCycle.
Ex you use 12bits which the conversion is about 12.5Cycles and use Sampling time 1.5Cycles 
the total is 14cycle for single conversion and if you use ADC Clock is 35MHz, you will got 35MHz/14Cycles -> 2.5Msps.

Sampling and conversion, they use ADC Clock so you can add them together and find total time later.

[luke514]

So I suppose my calculation 1a) is correct ... I gave an example just so I wouldn't make a mistake.

[Tinnagit · Accepted solution]

may I got what you want about 166us sampling time.
Do you want to make ADC sampling 6Ksps?

if I have correct understanding, it's not about Tsampling and Tconvesion.
you just need ADC trigger every 166.6us so you just need set some timer to trigger ADC every 166.6us but your ADC need to have Tsampling+Tconversion less than 166.6us every much because it also need space time to process another thing while processing.

which ADC had support timer trigger already.  

[luke514]

I was looking for exactly this answer you gave, evidently I had not expressed myself well in my question. I was convinced that how often to sample with the ADC was decided right in the "Tsample" and "Tconv" parameters of the ADC, in fact I need to sample an input signal at about 6kHz --> 166.6us

But you told me that a TIMER is used (i.e. set it with interrupt every 166.6us).

Thank you very much, it is much clearer now!

1) Why do you say "Tsamp+Tconv less than 166.6us"?? It should be "Tconv less than 166.6us" since Tconv already contains Tsampl inside it .. right?

2) So I have to make sure that Tconv<166.6us .. and I set it by specifying an appropriate number of cycles in "Tsample" parameter of the ADC in the .ioc file and taking into account those +12 cycles in the formula:

[Tinnagit]

it's signal sampling process.
your point is you want to get data from signal every 166.66us. so it's sampling frequency 6KHz or 6Ksps.
The simple way is set timer to trigger at 6KHz (divided from APB Clock) and start to sampling and get data from ADC so You have to do this process finish before next interrupt was happen because if it's not finished before, your system is going to stop.
So this reason for why do I recommend to use Ttotal less than 166.66us. You need time to do another thing too.
and you can use Timer to set sampling frequency which it's not relate directly to Ttotal.  

this may useful for you to understand relation between ADC and Timer
Hands-On with STM32 Timers: Trigger Periodic ADC Conversions - YouTube