Why does the CCR value not Updated?

[BoboyeOkeya]

Hi All,

I would appreciate your help with this problem.

I am presently trying to implement the PWM scheme PWMON as shown in figure below.

I have set the polarity of the timer's main and complementary output to be LOW. And it runs on PWM Mode1.

And then applied the Pulse value to the CCR to get the first step. And for the next step, which is meant to be fully ON, I have applied the (full timer period(ARR)+2). Which would mean that ideally, the OCREF should be high as long as the CCR value is greater than then ARR value. but this is not the case.

 

From the image, the second step is meant to be fully ON, but its not.

 

Please can someone point me in the direction to look

[Laurent Ca...]

Dear @BoboyeOkeya​ 

Welcome to the STM32 Community

Could you give more details to the STM32 Community about your setup -the material you use- ?

(HW and also SW: CPU(s), tools and versions, board(s), motor(s) and so on)

And more especially did you use STM32 MC tools (such as MC_suite, STM32 MC Motor Profile, STM32 MC SDK, STM32 MC Workbench, the used example, the origin of the base of your application source code, and so on)?

Best regards

[Tesla DeLorean]

Depending on TIM and Preload settings, the CCRx / ARR can be held in shadow register that get latched at the Update Event

[BoboyeOkeya]

Hi De Lorean,

Please do you mind shedding more light on this. How exactly do I ensure that this shadow register doesnt latch the CCR values?

I think the major problem is the CCRx not ARR though.

What thinkest thou Tesla?