MCSDK 5.7.3 r3_f30x_pwm_curr_fdbk.c error with STM32F302VC.

[SpinKernel]

 Keep inserting

    if ( TIMx == TIM1 )
    {
      /* TIM1 Counter Clock stopped when the core is halted */
      LL_DBGMCU_APB2_GRP1_FreezePeriph( LL_DBGMCU_APB2_GRP1_TIM1_STOP );
    }
    else
    {
      /* TIM8 Counter Clock stopped when the core is halted */
      LL_DBGMCU_APB2_GRP1_FreezePeriph( LL_DBGMCU_APB2_GRP1_TIM8_STOP );
    }
    if ( OPAMPParams != NULL )
    {
      LL_OPAMP_Enable( OPAMPParams->OPAMPx_1 );
      LL_OPAMP_Enable( OPAMPParams->OPAMPx_2 );
    }

but  LL_DBGMCU_APB2_GRP1_TIM8_STOP doesn't exist. Every time I "generate" code i have to go in an comment out this line since I don't have a TM8 thus in stm32f302xc.h #define DBGMCU_APB2_FZ_DBG_TIM1_STOP isn't present.

Someone at STM Please LMK how to prevent MX from generating this?

[GMA]

Dear SpinKernel,

Firstly, we would like to sincerely apologize for the delay in replying to your post.
Thank you for your report. Some LL_DBGMCU_APB2_GRP1_TIM8_STOP usage is already TIM8 definition dependent and will it be fully corrected on WB6.2.1.