I am using stm32f401VE controller to drive IM using spwm and open loop V/F method. I configured carrier frequency as 4KHZ and creating sine signal in TIM2 which is of 100usec.computation of compare count for the sine wave is happening in TIM1 update event which should be theoretically 250usec.
I configured TIM1 as clock 84MHz,prescale value is 7, PWM mode 2, centre aligned mode. I calculated value for 2625 for getting period 250usec or half 125usec for centre aligned method(1312). Interrupt priority is set as TIM1 is 0 and TIM2 is 1.
Execution time of ISR TIM1 is 12usec and TIM2 is 36usec
Following are my observations
1. Update event is happening in 124usec which supposed to be at 125usec
2. If i compute compare count value in TIM2 sometimes i missed update event.
3.if i use edge aligned counter (UP counter), output voltages are imbalanced by 10-15 volts and current is by 1-2Amp.
4. If i use centre aligned counter (up down counter) voltage imbalance is 5 volt and current imbalance is 0.5Amp which increases as load increases.
I tried other combinations of count value by changing prescale value but result is same,
I am unable to figure out the cause of imbalancing?
Please give your valuable suggestion to resolve it.
