USB_ISTR Register User Manual Ambiguity

[David Ledger]

I have a USB development project that entails the creation of a composite USB device. To integrate it with third party USB stacks I'm developing an interface for the low level USB functionality.

In the RM0360 user manual, Page 697 the DIR bit is described:

This bit is written by the hardware according to the direction of the successful transaction,

which generated the interrupt request.

If DIR bit=0, CTR_TX bit is set in the USB_EPnR register related to the interrupting endpoint.

The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host

PC).

If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX are set in the USB_EPnR register

related to the interrupting endpoint. The interrupting transaction is of OUT type (data

received by the USB peripheral from the host PC) or two pending transactions are waiting to

be processed.

This information can be used by the application software to access the USB_EPnR bits

related to the triggering transaction since it represents the direction having the interrupt

pending. This bit is read-only.

The first bold sentance to me seems ambigious, which does it mean:

(DIR == 0) and (CTR_TX == 1)

(DIR == 0) or (CTR_TX == 1)

The second sentance also seems ambigious, but less so, does it mean:

(DIR == 1) or (CTR_RX == 1) or (CTR_TX == 1and CTR_RX == 1)

(DIR == 1) and ((CTR_RX == 1) or (CTR_TX == 1 and CTR_RX == 1))

((DIR == 1) and (CTR_RX == 1)) or (CTR_TX == 1 and CTR_RX == 1)

In the second case, which I suspect is the answer, when is the DIR bit actually useful.

I have to get this right because I have no equipment to analyse the signals, only software solutions.

Maybe ST have written this in a formal way that to me is ambigious but is actually well defined... Anyway, anybody have any insight into the true meaning of that section?

[waclawek.jan · Accepted solution]

Value of DIR bit is a *consequence* of how the CTR_RX and CTR_TX bits are set in the highest-priority USB_EPnR (see EP_ID description) with any of these bits set.

In pseudocode, the USB IP does this after every transaction:

for (endpoint = highest to lowest priority) {
  if (CTR_RX || CTR_TX) {
    EP_ID = endpoint;
    CTR = 1;
    if (CTR_RX) DIR=1; else /* only CTR_TX is set */ DIR=0;
    break;
  }
}

JW

[David Ledger]

Thankyou!

Why didn't they write that lol.

In that case it should say:

DIR is set to 0 when CTR_TX bit is set in the USB_EPnR register related to the interrupting endpoint.

and

DIR is set to 1 when, CTR_RX bit or both CTR_TX/CTR_RX are set in the USB_EPnR register

related to the interrupting endpoint.

Thankyou for an answer that can be understood!

[waclawek.jan]

It's written from the application/software/programmer's point of view, not the hardware point of view. It says, "Hey, programmer, read DIR, if it is 0, expect CTR_TX bit being set, if 1, expect CTR_RX or both bits to be set".

JW