Unions and flash access

[Clyde_S]

I am wishing to write two floating point values to flash memory at time.  I understand it is best to write 64 bits at a time, hence my writing two floats at once.

This question is about using a union to structure the data. This code won't compile for the STM32L412KB.  Could someone please show me where I am going wrong? error on line 17.  Thanks.

struct dual {
          float v1;
          float v2;
};

struct dual two_readings = {1.23, 4.56};

union gemini
{
        struct dual left;
        uint64_t right;
};

union gemini value;


value.right=0;

[TDK]

@gbm Thank you for the correction. I was so sure you were wrong, which led down an interesting rabbit hole.

From my read of the linked thread, the STRD instruction can be interrupted mid-way through by an ISR, and then restarted in full again, leading to 3x 32-bit writes. Which would lead to a PGSERR error. Maybe that's why HAL treats it as 2x 32-bit writes. Or maybe they just got lucky.

https://community.arm.com/support-forums/f/architectures-and-processors-forum/4201/c-c-atomic-operation-on-arm9-and-arm-cortex-m4

Copying it here in case the page dies.

So yes, it exists. It's not atomic. And it will make 0 difference in flash endurance.

[gbm]

@TDK There is something wrong with the statement above. I did a quick research of ARM architecture documents and I couldn't find any trace of LDRD/STRD being interruptible. LDM/STM can surely be interrupted, then continued after interrupt return. Making the LDRD/STRD interruptible would only speed up the interrupt response by one cycle - not worth it, considering the added complexity.

This is not to say they cannot be aborted and restarted after ISR return, it's just I can't see any reliable trace of this possibility in ARM documents - v7-M RefMan and CM4 TechRefMan. I believe such feature would be described in the manuals if it existed; note that LDM & STM abort/restart behavior is fully documented.

The (lack of) capability of LDRD/STRD restart is not strictly related to their lack of atomicity claimed in RefMan. I personally believe these instructions are atomic at processor level but the sequence of memory accesses don't have to be atomic at system (bus matrix) level. I couldn't find any suggestion that they might not be atomic at CPU level. Ok, maybe I am blind. ;)

[TDK · Accepted solution]

@gbm I felt this was getting a bit too off-topic for the OP which is concerned about flash endurance so I posted a new questions and answer here:

How atomic are the STRD/LDRD instructions on Corte... - STMicroelectronics Community

Let me know if I've misinterpreted the result.

[Pavel A.]

Situation with STM32L4 seems more complicated as it supports "fast programming mode".

Simple 64-bit programming is demonstrated in the HAL library (function FLASH_Program_DoubleWord):

https://github.com/STMicroelectronics/stm32l4xx-hal-driver/blob/f8e66b7f8db10809f91a4360c154b6304fab06ba/Src/stm32l4xx_hal_flash.c#L705

It splits the uint64 data to two uint32 and writes them successfully (of course no STRD's there). Looks like the flash controller has internal buffer which accumulates the 64-bit value before programming.

But then there's function FLASH_Program_Fast, it writes 32 or 64 64-bit words, depending on the STM32L4 model, at once, with interrupts disabled. Also without STRD's.

Not sure how useful this can be to the OP.

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