STM32N6 SPI5 + GPDMA TX: MOSI stays low, CPU TX works

[bei]

Hello,

I am testing SPI5 TX by GPDMA on an STM32N6 device and I found behavior that seems inconsistent with the reference manual.

MCU / Environment

• MCU: STM32N647X0H

• Toolchain: STM32CubeIDE 2.1.1

• CubeMX / CubeN6 version: STM32Cube_FW_N6_V1.3.0

Issue summary
I configured SPI5 as:

• Master

• Simplex TX-only

• Software NSS

• SSI set high

I configured GPDMA1 Channel0 as:

• Memory-to-peripheral

• Source = TX buffer

• Destination = SPI5->TXDR

• Transfer length = 8 bytes

• TX pattern = A5 5A A5 5A A5 5A A5 5A

Observed behavior

• If I write data directly to SPI5->TXDR by CPU, MOSI outputs correctly.

• If I use GPDMA for SPI5 TX, SCK may appear, but MOSI stays low / no valid TX data is output.

• I reduced the project to a minimal LL test case and the behavior is reproducible.

What I already verified

1. Same SPI5 pin configuration is used in both tests.

2. CPU TX path works with the same SPI configuration.

3. TX buffer content is correct in memory (A5 5A ...).

4. DMA source address points to the TX buffer.

5. DMA destination address points to SPI5->TXDR.

6. DCache is disabled during this test.

7. I also tested simplex TX-only to reduce variables.

Expectation
According to RM0486, SPI TX DMA requests should be generated when TXP is set, and DMA should write data into SPI_TXDR.

Question
Could ST please confirm:

1. whether this is an expected limitation on STM32N6 SPI5 + GPDMA,

2. whether there is any required configuration not mentioned clearly in RM / Cube-generated code,

3. or whether this may be a silicon / HAL / LL issue?

Additional information
I can provide:

• minimal project

• register dump

• oscilloscope screenshots

• CPU TX working waveform vs DMA TX failing waveform

The attached file is the compressed project archive for this minimal test case.

Thank you.

[ANJS]

Hello
It may be a security issue. By default the GPDMA is non-secure and unprivileged, if it tries to access memory or peripherals which attributes is secured/privileged, it will not work (eventually an ILLAcc if IAC is enabled).
GPDMA is RIF-aware. You can configure its security attribute with 
HAL_DMA_ConfigChannelAttributes()
Best regards
ANJS

[Saket_Om]

Hello @bei 

Please refer to the example below:

STM32CubeN6/Projects/NUCLEO-N657X0-Q/Examples_LL/SPI at main · STMicroelectronics/STM32CubeN6