STM32H745 not works with KSZ8081RNA

[IOvch]

Hello!

I am trying to run ping on my board with STM32H745 (similar to NUCLEO-H745ZI-Q). Instead of the standard LAN8742, I have to use KSZ8081RNA. On the advice of @Piranha​ and @Pavel A.​ in other branches, I leave almost everything as it is in the LAN8742.c driver, I change only some registers in order for initialization to be successful (I only needed to change the LAN8742_GetLinkState function). I can read and write KSZ8081RNA registers. I see in debugging a link change when connecting/disconnecting an ethernet cable.

But ping data packets (ICMP) are still not coming to me.

The program does not pass /* Check if descriptor is not owned by DMA */ check (HAL_ETH_Read Data in the file stm32h7xx_hal_et.c line 1063) due to the values of the descriptors heth->RxDescList.RxDesc. It is equal to 0x81000000. In another, working project, it is equal to 0x3401003С.

Most likely, I did not fully initialize correctly, because the same project worked on NUCLEO-H745ZI-Q before the changes. I don't fully understand how packets are received via DMA. But what should I change except LAN8742_Init function?

[Pavel A.]

I don't have STM32H745 but 0x81000000 does not look like a valid internal RAM address.

0x340100xx is a valid address.

[Piranha]

Are you using the newest HAL drivers from CubeH7 firmware package v1.10?

Have you defined the following PHY registers and bit fields with the values for your PHY chip?

https://community.st.com/s/question/0D53W000015bQsFSAU/cant-get-f746zg-nucleo-ethernet-to-work-with-the-lwip-example-on-cubeide

[Piranha]

RDES3 is not a memory address, but just a configuration word. 0x81000000 is an OWN and BUF1V bits, which seems to be OK.

[IOvch]

Thanks for your answer! Yes, I have read that v1.10 is first actually working and started work with ethernet (for the first time) from this version.

No, I can't find where I should change them. It doesn't look like it should be in lan8742.c/h or in stm32h7xx_hal_eth.c/h

[Piranha]

It was in a stm32h7xx_hal_conf.h, but seems that it's removed now. So now you have to adapt the PHY driver. Adapting all of the defines starting with LAN8742_PHYSCSR... in lan8742.h should be enough.

[IOvch]

Thank you all for your help! it turned out that everything was fine with the code, there was a solder defect with CRS_DV pin. At least we now know one of the symptoms of such a problem. I attach my project if someone needs it.

[Piranha · Accepted solution]

You didn't listen to me... Your code uses the constant PHY capability bits as if those would show the selected mode. Instead you have to use the Operation Mode Indication bits in register PHY Control 1 (0x1E). The lan8742.c file shouldn't require modification at all - read my other comment.

[IOvch]

You're right as always, yesterday I was just very glad that it finally worked somehow. I have improved this minimal project on the changes in the lan8742.h file only and the correct speed indication. This does not cover full-fledged work, just minimal functionality test.

[Piranha]

Seems to be correct now. :)