Hello
I am using STM32H743XIH6 for Digital Power control. System clock 400MHz. ADC work clock is 36Mhz from pll2 divison. I use a external 36KHz square wave with 50% duty cycle input to GPIO_G11 to trig ADC1 and ADC3 simultaneously to converse regular channel and DMA1 stream0 and DMA1 stream2 to move result to SRAM erea in AXI SRAM.I config ADC1 converse 8 channel spending 160clokcs totally, and ADC3 converse the other 8 channel also 160 clokcs.I read ADC1 and ADC3 sample result data in DMA1 stream2 converse complete interrupt handler.
ADC1 seventh channel analog input is changed by a analog switch every interrupt.
Also, ADC3 seventh channel analog input is changed by a analog switch every interrupt. Because I controll the external analog switching in every interrupt handle.
I met a problem: my hardware running correct in many many days, but one day ADC1 seventh channel adc converse result I read from sram in interrupt handler is exchange with last data. But ADC3's is always correct.
So, Is there are limit ? ADC3 is fast than ADC1？ADC1 DMA move is slower than read data in interrupt？Is there something do with DSB() instruction?
I also see device errata 2.2.9: Reading from AXI SRAM may lead to data read corruption. Is that the reason? Could you explain?
This sampling problem cause our High Power three-phase electric product blow up.
We desperately need a explain.Thanks.
