2024-10-02 06:50 AM - last edited on 2024-10-02 06:53 AM by SofLit
Hello.Im tring to make an rcc configuration for my stm32f429i discovery board for 48mhz HCLK with ahb1 prescaler is 1.According to STM32CUBEMX ,pllm is 4,plln is 192,pllp is 8 for 8Mhz HSE.wHEN I DEBUG THE CODE,HCLK still showing 180Mhz and this never changes with different configurations.I have tried everything but no result.You have any idea?
#include "stm32f4xx.h"
#include "stm32f429i_discovery.h"
void rcc_config(void) {
RCC->CR=0x00000000; //resetting Control register
RCC->CR |= (1<<16); //HSEON enabled
while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) !=SET); //wait until flag rises
RCC->APB1ENR |= 1<<28;
PWR->CR |= 3<<14;
FLASH->ACR = (1<<8) | (1<<9)| (1<<10)| (5<<0);
RCC->CFGR &= ~(1<<4);
RCC->CR |= (1 << 19); // CSS On
RCC->PLLCFGR= 0x24003010; //Resetting PLL register
//This function must be used only when the main PLL is disabled.
RCC->CR |= (0<<24); //Disabling Main PLL
RCC->PLLCFGR |= (0<<5) | (0<<4) | (0<<3) | (1<<2) | (0<<1) | (0<<0);//pllm value is 4
RCC->PLLCFGR |= (0<<6) |(0<<7) | (0<<8) | (0<<9) | (0<<10) | (0<<11) | (1<<12) | (1<<13) | (0<<14);//plln is 192
RCC->PLLCFGR |= (1<<16) | (1<<17);//pllp is 8
RCC->PLLCFGR |= (1<<22); //PLL (PLLI2S) entry clock source is HSE
RCC->CR |= (0<<24); //Enabling Main PLL
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) !=SET);
RCC->CFGR |= (0<<0) | (1<<1);
while(!(RCC->CFGR & (2<<2)));
//After enabling the main PLL, the application software should wait on
//PLLRDY flag to be set indicating that PLL clock is stable and can
//be used as system clock source.
}
int main(void)
{
RCC_ClocksTypeDef rcc_clocks_struct;
rcc_config();
STM_EVAL_LEDInit(LED3);
STM_EVAL_LEDInit(LED4);
STM_EVAL_LEDOn(LED3);
STM_EVAL_LEDOn(LED4);
while (1)
{
SystemCoreClockUpdate();
RCC_GetClocksFreq(&rcc_clocks_struct);
}
}
uint32_t sEE_TIMEOUT_UserCallback(void)
{
while (1)
{
}
}
2024-10-03 09:33 AM
Sorry, just joking : because @TDK wrote : > This code seems artificially generated. <
But: why dont you use Cube/HAL , to see "how its done" ?
(Even if you dont like it ... )
2024-10-03 10:05 AM
That, plus the issues with bit manipulation (or'ing with 0, failing to reset bits). I did not mean to offend. Stepping through the code in a debugger may allow you to spot these issues a bit faster. Cheers.