I have custom hardware with a STMF407VET6 connecting to a ethernet switch via the MII interface.
I am using STMCUBEIDE 1.15.1 to generate the basic code. For debugging I am using a barebones configuration for the ethernet connectivity and a GPIO to control the ethernet switch reset to ensure the strapping pins are properly loaded. FreeRTOS with LWIP [BSP = MII].
When I run the debugger
There is a HAL_ERROR returned in the HAL_ETH_init() function at this point.
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
/* Dummy read to sync SYSCFG with ETH */
(void)SYSCFG->PMC;
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
{
if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
/* Set State as Error */
heth->gState = HAL_ETH_STATE_ERROR;
/* Return Error */
return HAL_ERROR; <<< Error returned here. >>>
I have forced the switch MII interface to 100M / Full duplex via strapping pins.
I have verified
Voltages are nominal can clean.
There are clean 25MHz clocks on RXCLK PA1 and TXCLK PC3 right after HAL_GPIO_init()
In ethernet.c, void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle), __HAL_RCC_ETH_CLK_ENABLE(); properly sets all the MAC clock enables in RCC->AHB1ENR.
Observations
When I comment out the software reset check I can transmit packets if I enable SW CRC generation.
Reading all MAC counters show they are frozen.
The Software reset bit is stuck high before the write.
Reference manual states "The application has to set the MII/RMII mode while the Ethernet controller is under reset or before enabling the clocks.", but it looks like the clocks are enabled before MII/RMII mode is set. I tried changing the order but that did not change the HAL_ERROR behavior.
Is there anything else I could be missing on the hardware side or ideas how to debug?
Thinking about it, since the MAC speed is not configured before this check is called could it be the ethernet MACs are in 10Mbps mode and I am feeding 25MHz (100Mbps) and that is the causing a software reset failure?
Does ST have any LQFP package based hardware that supports Ethernet MII PHYs for reference?
I have seen others have got this to work, but I am stuck. Thanks for any help
