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STM32F407 ETH Fatal Bus Error

Jerry邵
Associate II

During stress testing involving repeated startup and shutdown, a fatal error was encountered in the STM32F407 Ethernet (ETH) module.

The issue was observed during the startup phase, where a problem occurred in the ETH DMA. The DMASR register indicated a Fatal Bus Error.

The following are the ETH register values captured when the error occurred:

MACCR : 0x0200CE0C
MACFFR : 0x00000000
MACHTHR : 0x00000000
MACHTLR : 0x00000000
MACMIIAR : 0x000007D0
MACMIIDR : 0x00001058
MACFCR : 0x00000080
MACVLANTR : 0x00000000
MACRWUFFR : 0x00000000
MACPMTCSR : 0x00000000
MACDBGR : 0x00000000
MACSR : 0x00000000
MACIMR : 0x00000208
MACA0HR : 0x80000103
MACA0LR : 0x0AE18000
MACA1HR : 0x0000FFFF
MACA1LR : 0xFFFFFFFF
MACA2HR : 0x0000FFFF
MACA2LR : 0xFFFFFFFF
MACA3HR : 0x0000FFFF
MACA3LR : 0xFFFFFFFF
MMCCR : 0x00000000
MMCRIR : 0x00000000
MMCTIR : 0x00000000
MMCRIMR : 0x00020060
MMCTIMR : 0x0020C000
MMCTGFSCCR : 0x00000000
MMCTGFMSCCR : 0x00000000
MMCTGFCR : 0x00000001
MMCRFCECR : 0x00000000
MMCRFAECR : 0x00000000
MMCRGUFCR : 0x00000003
PTPTSCR : 0x00002000
PTPSSIR : 0x00000000
PTPTSHR : 0x00000000
PTPTSLR : 0x00000000
PTPTSHUR : 0x00000000
PTPTSLUR : 0x00000000
PTPTSAR : 0x00000000
PTPTTHR : 0x00000000
PTPTTLR : 0x00000000
 PTPTSSR : 0x00000000
DMABMR : 0x02C12080
DMATPDR : 0x00000000
DMARPDR : 0x00000000
DMARDLAR : 0x20005554
DMATDLAR : 0x200055F4
 DMASR : 0x0189A4C2
DMAOMR : 0x02202006
DMAIER : 0x000020C1
DMAMFBOCR : 0x00002773
DMARSWTR : 0x00000000
DMACHTDR : 0x2000561C
DMACHRDR : 0x20005554
DMACHTBAR : 0x00000000
DMACHRBAR : 0x20004F48␍␊
5 REPLIES 5
TDK
Super User

Repeatedly turning on and off the device seems like it might introduce some issues. What is the expectation? A watchdog should allow you to recover from unexpected events.

If you feel a post has answered your question, please click "Accept as Solution".
Jerry邵
Associate II

1. The code was generated using STM32CubeMX

2. The STM32Cube FW_F4 firmware package version 1.28.1 was used.

We have already tried resetting the ETH module in the monitoring program, including both the MAC and DMA. However, because LWIP is tightly coupled with the ETH driver, this approach is not ideal.

We would like to understand the root cause of this issue and resolve it fundamentally.

During repeated device reboot testing, the issue occurs approximately once every few hundred reboots. Although it is a relatively rare and intermittent phenomenon, it is unacceptable for mass-produced products.

Jerry邵
Associate II
To rule out address access issues, I checked whether the address of q->payload in the following code falls within the range 0x20000000–0x20020000.
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
  uint32_t i = 0U;
  struct pbuf *q = NULL;
  err_t errval = ERR_OK;
  ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};

  memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));

  for(q = p; q != NULL; q = q->next)
  {
    if(i >= ETH_TX_DESC_CNT)
      return ERR_IF;

    Txbuffer[i].buffer = q->payload;
    Txbuffer[i].len = q->len;

    if(i>0)
    {
      Txbuffer[i-1].next = &Txbuffer[i];
    }

    if(q->next == NULL)
    {
      Txbuffer[i].next = NULL;
   }

   i++;
 }

TxConfig.Length = p->tot_len;
TxConfig.TxBuffer = Txbuffer;
TxConfig.pData = p;

pbuf_ref(p);

do
{
if(HAL_ETH_Transmit_IT(&heth, &TxConfig) == HAL_OK)
{
errval = ERR_OK;
}
else
{

if(HAL_ETH_GetError(&heth) & HAL_ETH_ERROR_BUSY)
{
/* Wait for descriptors to become available */
osSemaphoreAcquire(TxPktSemaphore, ETHIF_TX_TIMEOUT);
HAL_ETH_ReleaseTxPacket(&heth);
errval = ERR_BUF;
}
else
{
/* Other error */
pbuf_free(p);
errval = ERR_IF;
}
}
}while(errval == ERR_BUF);

return errval;
}