Hi All,
I have recently joined a new company and I currently responsible for the Firmware design on a new product that has been externally advised that it should be rated as Class C, with regards the following standards (IEC-60730 and IEC-60335). The main and only processor on the Safety Board in question is an STM32G0C1.
Being new to this level of code complexity, where Class C as far as I can see and correct me if I am wrong is basically equivalent to the SIL - 3 standard. My main goal is to try and achieve compliance with the existing one processor design.
At the moment from my research ST can provide me with Class B safety libraries, but I was hoping to fill in the gaps, with a mixture of hardware and software elements. I am aware that the STM32G0 series has ECC protected Flash, so that is a plus, along with hardware CRC for memory integrity and dual watchdogs etc.
However I am currently unsure how I can comply with the address decoding section, which means testing the instruction set, along with other criteria, that is additional to Class B.
So I was hoping to get some much appreciated advice from any Engineers out there that have managed to achieve this compliance standard with a similar processor on its own.
My research options at the moment are telling me that I really need two processors both running the Class B libraries that check each other to really get me over the line. Unless you guys know different...fingers crossed.
Thanks in advance!
Pete
