Hi FAEs and the community,
On a L151 the SPI block has a strange behavior.
Some time to time it generates 8 clock cycles more on a read (if I use size 8 bits) or 16 bits (if I use size 16 bits).
My target is a 16 bits based half duplex SPI device.
Thus it introduces a shift on the next read and messing up everything...
I use the HAL (HAL_SPI_Receive and HAL_SPI_Transmit).
Withe a prescaler at SPI_BAUDRATEPRESCALER_128 (means 250Khz) I have few errors.
If I go up to SPI_BAUDRATEPRESCALER_64 (in spec according the stm32l1xx_hal_spi.c file) then the error is immediate...
Does someone has seen this behavior before ? Is there a fix ?
Is there a way to flush the RX fifo datas (if any) from this IP (and I have a work around) ?
Thanks a lot
Regards
Lionel.
