Malfunction Web Server using NetXDuo + FileX

[JongOk Baek]

Hello,

I am implementing a Web Server in my STM32H743 Board.

I have referenced the example implemented in STM32H735G-DK board.

Refer to the below

https://github.com/STMicroelectronics/x-cube-azrtos-h7/tree/main/Projects/STM32H735G-DK/Applications/NetXDuo/Nx_WebServer

(AzureRTOS, NetXDuo, FileX using microSD)

But I changed the memory pool location of D1(AXI-RAM) to D2(SRAM1, SRAM2).

  .tcp_sec (NOLOAD) : {

    . = ABSOLUTE(0x30000000);
    *(.RxDescripSection)

    . = ABSOLUTE(0x30000060);
    *(.TxDescripSection)

  } >RAM_D2

.nx_data (NOLOAD):
 {
    . = ABSOLUTE(0x30000100);
    *(.NxServerPoolSection)

    . = ABSOLUTE(0x30004100);
    *(.NetXPoolSection)

 } >RAM_D2

In this state, the web page does not function properly. The symptoms are similar to this in the link below.

https://community.st.com/t5/stm32-mcus-embedded-software/stm32h735g-dk-takes-a-long-time-to-open-the-web-page/td-p/797153

I restored that part back to the D1 domain.

    .tcp_sec (NOLOAD) : {

    . = ABSOLUTE(0x24030000);
    *(.RxDescripSection)

    . = ABSOLUTE(0x24030060);
    *(.TxDescripSection)

  } >RAM_D1

.nx_data (NOLOAD):
 {
    . = ABSOLUTE(0x24030100);
    *(.NxServerPoolSection)

    . = ABSOLUTE(0x24034100);
    *(.NetXPoolSection)

 } >RAM_D1

Of cause I also changed the MPU settings.

After that it works normally.

I wonder what the cause is.

[mbrossett · Accepted solution]

I think the issue may be that the SDMMC1 peripheral does not have access the AHB SRAM. Take a look at the System Architecture table and diagram in the reference manual. 

[mbarg.1]

We found that there is a limitation in the example you are using - it process only one connectiona at a time and does not close connecton untill timeout or browser reset. Browser amost of the time open multiple connections to server and that create a bottleneck in MPU sw.

We had to re-write part of server code to get rid of that, but we were able to get great performances in dual mode (ip 4+6).

You can check connecting http://o6.mb-international.net/orto.html ipv6 or http://a.mb-international.net:9743:/orto.html for ipv4 - all running on NUCLEO-h743, using internal storage (in this case, but works also with FX + USBX usb drive) plus websockets binary or JSON, saving logs on removable usb devices ...

Mike

[JongOk Baek]

Hi mbrossett,

Thanks for your reply.

I've been looking at 'System Architecture' and considering various directions, but I haven't considered what you mentioned.

Ethernet MAC - SRAM1/SRAM2/SRAM3 : 

DMA1 - SRAM1/SRAM2/SRAM3 : 

DMA2 - SRAM1/SRAM2/SRAM3 : 

Because of this part, I allocated NetX Pool to D2 domain area.

As of now, what you said seems credible.

Best regards,

[mbrossett]

The SDMMC and Eth MAC both have their own internal dedicated DMAs and do not rely on DMA1 or DMA2. 

If you didn't already have the hardware designed you could use SDMMC2 as it is located in the AHB D2 domain. Another option might be to use the MDMA for interfacing between the SDMMC1 and AHB SRAM. Otherwise just use the AXI SRAM as the SDMMC1 and Eth MAC have access to it. 

[JongOk Baek]

Yeah,

I will be testing to determine the cause more clearly.

(using MDMA(SDMMC1 - SRAM(in D2)) you mentioned.)

Thanks for your reply.