LwIP on the CM4 core of a dual core STM32H7?

[WLear]

Has anyone been successful using CubeMX to create a CubeIDE bare metal project with Ethernet/LwIP running on the CM4 core of a dual-core STM32H7 processor?

If so, I'd greatly appreciate any pointers or examples you can share.

[EOzde.1]

Hi,

The below link might help you a lot. Have a great day.

https://community.st.com/s/article/How-to-create-project-for-STM32H7-with-Ethernet-and-LwIP-stack-working

[EOzde.1 · Accepted solution]

1. When running the stack on Cortex-M4, the buffers can be placed at the same address (0x30040000), but it is better to place them at 0x10040000 which is alias for the same address. This alias is accessible by Cortex-M4 D-bus and helps to utilize the Harvard architecture.
2. When not using FreeRTOS, the Ethernet interrupt should be disabled and MX_LWIP_Process should be called periodically (in main loop).

[WLear]

Thanks! I had not even thought about using the aliased address space for the buffers - excellent idea.

I've seen, and successfully used the various examples for the M7 core, but they all focus primarily on the intricacies of dealing with the M7 dCache - of little interest on the M4.