The conclusion is that setting filters and interrupts on FIFO0 leads to exception handling
FDCAN1_IT1_IRQHandler.
The reason for this behavior is an error in the file. startup_stm32g431cbtx.s
ERROR
..
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.wordh FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
..
This is how it should be
...
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
...
As an example, the code that I use is for testing so that there are no questions).
void CAN_Config(void) {
FDCAN_GlobalTypeDef *CAN = FDCAN1;
uint32_t *filterRAM = (uint32_t *)RAMBaseFDCAN1;
// Включение тактирования для CAN
RCC->APB1ENR1 |= RCC_APB1ENR1_FDCANEN;
RCC->CCIPR &= ~RCC_CCIPR_FDCANSEL;
// PLL "Q" for FDCAN
RCC->CCIPR |= (0x1 << RCC_CCIPR_FDCANSEL_Pos);
// Init FDCAN module
CAN->CCCR |= FDCAN_CCCR_INIT;
while (!(CAN->CCCR & FDCAN_CCCR_INIT));
CAN->CCCR |= FDCAN_CCCR_CCE;
/*
Baudrate NSJW NBRP NTSEG1 NTSEG2 FDCAN_NBTP (uint32)
125000 1 640 543 95 0x21F5F
250000 1 320 271 47 0x10F2F
500000 2 160 67 12 0x08617
800000 1 100 84 14 0x0540E
1000000 1 80 67 11 0x0430B
*/
// Set the nominal bit timing register
CAN->NBTP = (1 << FDCAN_NBTP_NSJW_Pos) |
(1 << FDCAN_NBTP_NBRP_Pos) |
(66 << FDCAN_NBTP_NTSEG1_Pos)|
(11 << FDCAN_NBTP_NTSEG2_Pos);
// Clear message RAM
for(uint8_t i=0;i< 212;i++){filterRAM[i] = 0;};
/* FDCAN global filter configuration register (FDCAN_RXGFC)
Address offset: 0x0080
Reset value: 0x0000 0000
*/
//CAN->RXGFC = STDfilter_n(2)|EXTfilter_n(0)|ANFS_Reject_rx|ANFE_Reject_rx;
CAN->RXGFC = (2<<16)|(2<<4)|(2 << 2);//
// ID filters 100 and 80
// filterRAM[0] = STDfilterID_DUAL | STDfilterRxFIFO0 | STDfilterID1(0x100) | STDfilterID2(0x80);
filterRAM[0] = (1 << 30) | (1 << 27) | (0x100 << 16) | 80;
// Включить прерывания в FDCAN FIFO
CAN->IE |= 3; // FDCAN_IE_RF0NE_| RF0FE
CAN->ILS |= 1; // RXFIFO0: RX FIFO bit grouping the following interruption
CAN->ILE |= 3; // Enable IT0
// Normal MODE
CAN->CCCR &= ~FDCAN_CCCR_INIT; // Выход из режима инициализации
while (CAN->CCCR & FDCAN_CCCR_INIT);
NVIC_EnableIRQ(FDCAN1_IT0_IRQn);;
NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
}
It took me several hours to understand that someone had screwed up.(
RM0440
Sometimes it blows my mind too))
