STM32G431 ADC Glitches when triggered by timer

[David Koster]

I have an STM32G431 doing FOC on a little gimbal motor, but am getting strange noise on the current sense ADC when it's being triggered by TIM3. It shows up as random spikes, which values always end up being dividable by 8. 

Weird thing is, if I have the ADC set to oversample, it will average out these spikes. While I'm 100% sure it's a digital artifact, not measured noise. That would never ever all end up with the last 3 bits being "000". 

Here's a direct comparison by the ADC being triggered by TIM3's TRGO directly:

And changing nothing but starting the ADC through software in the TIM3 update event interrupt:

Does this ring a bell anywhere? I've been wrestling with this for days, but can't find a way to get rid of the artifacts while still triggering the ADC automatically. 

[TDK]

Typically happens if VREF+ is not stable. Motor noise will exacerbate the issue, though it doesn't seem to be the main cause here.

You could also try triggering on a CCx event rather than the update, though I don't expect different results.

[waclawek.jan]

As @TDK said, the prime suspect is VREF+, maybe through common-ground issues. While you see it to be purely digital issue due to several LSB being systematically all 0, an incorrectly decided 4th or 5th bit due to unstable (improperly stabilized or decoupled) VREF+ or ground noise can end up with exactly such result. There are reports of slope-measured-as-stairway cases confirming exactly this.

This can be exacerbated by the fact that ST - in an attempt to increase usable pin count - reduced power-supply and ground pins in the 'G4 line (they bragged about this back then), increasing their impedance and also the chance for various weird cross-coupling issues in analog, see the dedicated 'G4 ADC appnote.

JW

[David Koster]

Thank you for the replies @waclawek.jan and @TDK.

I had a look at VREF+ (and VDDA) on the scope, and they look quite solid. Measuring vrefint with ADC1 also only gives me a couple counts of noise. It's only ADC2 that has the issue, and only when triggered by the timer directly. While the VREF+ issue sounds relevant, I'm not sure how it would apply here. What do you think?

[waclawek.jan]

> I had a look at VREF+ (and VDDA) on the scope, and they look quite solid.

While you haven't provided absolute scale, you appear to talk about 3 bits of noise, i.e. around 5mV. These may also be very short pulses. Ground arrangement during measurement matters, too.

Also you talk about correlation with TIM3, so consider every event related to TIM3 (e.g. pins being driven). As @TDK said above, try to trigger ADC from TIM3 CC, with varying delay to Update.

JW