Ethernet software reset is not clearing

[vneff]

The Ethernet reset is not clearing (ETH_DMABMR_SR in DMABMR).
I am having a similar issue as others but have not seen a solution in the forum.
I am working with the stm3210c-eval board. I know it is no longer available; but it has a version of the processor that I wish to use and Ethernet support.
I verified that the Ethernet clocks are enabled in AHBENR:
RCC_AHBENR_ETHMACEN, RCC_AHBENR_ETHMACTXEN & RCC_AHBENR_ETHMACTXEN.
I verified that the port IO clocks are enabled.
The pins ETH_MDC, ETH_TXD2, ETH_TX_CLK, ETH_CRS, ETH_RX_CLK, ETH_MDIO, ETH_COL, ETH_TX_EN, ETH_TXD0, ETH_TXD1, ETH_TXD3, ETH_RX_DV, ETH_RXD0, ETH_RXD1, ETH_RXD2 & ETH_RXD3 pin's modes are set to GPIO_MODE_AF_PP.
And pin ETH_RX_ER is set to input, no pull.
I verified that there is a 25 mHz clock signal at PA1 & PC3.
It is configured for MII mode (MAPR AFIO_MAPR_MII_RMII_SEL = 0).
Note that the Ethernet link & activity LEDs are working.
Is there anything else I can check?

[Pavel A.]

IIRC this can indicate a problem with the PHY.

[waclawek.jan]

> The pins ETH_MDC, ETH_TXD2, ETH_TX_CLK, ETH_CRS, ETH_RX_CLK, ETH_MDIO, ETH_COL, ETH_TX_EN, ETH_TXD0, ETH_TXD1, ETH_TXD3, ETH_RX_DV, ETH_RXD0, ETH_RXD1, ETH_RXD2 & ETH_RXD3 pin's modes are set to GPIO_MODE_AF_PP.

The 'F1 has a rather strange GPIO arrangement. RM0008 says:

JW

[vneff]

If the mode is set to GPIO_MODE_AF_PP, the HAL does not control the input pull state.

The HAL_ETH_MspInit function does sometimes set

GPIO_InitStruct.Pull = GPIO_NOPULL

but HAL_GPIO_Init does not bother checking GPIO_InitStruct.Pull if mode = GPIO_MODE_AF_PP.

[waclawek.jan · Accepted solution]

The table above says you should set those pins to Input, not AF.

JW