Can STM32F207xx Generate 50MHz Clock for RMII Ethernet PHY ?

[martin]

Posted on August 29, 2013 at 04:24

With regard to the STM32F207ZET, on Page 30 of the current STM32F207xxx Datasheet (Doc ID 15818 Rev 9 Oct 2012) it says ''...the PHY is connected to the STM32F207xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F207xx''.

I understand this means the STM32F207xx can provide the 50MHz clock required by a PHY circuit operating in RMII mode.  But I can find no further reference to this, such as any details of how the STM32F207xx must be configured to enable this, or even which pin the 50MHz RMII Clock Signal will be output on.  However, on page 164 of the same datasheet the 50MHz signal is shown being provided by a seperate crystal oscillator.

So, is it possible to have the STM32F207xx provide the 50MHz Clock Signal required for a RMII PHY, or is the datasheet incorrect on Page 30 ?

If it is possible to have the STM32F207xx provide the 50MHz Clock Signal required for the RMII PHY, what documentation describes how to make use of this ?

Thanking you,

mai-au. #rmii #stm32f207xx #50mhz #ethernet

[Tesla DeLorean]

Posted on August 29, 2013 at 04:57

You'd have to run the F2 or F4 at a multiple of 50 MHz, then route a fractional PLL clock via MCO (PA8)

So F2 @ 50 or 100 MHz, F4 @ 50, 100 or 150 MHz Or just buy a crystal. You could use a 25 MHz crystal for HSE, and use a PHY taking 25 MHz also

[martin]

Posted on August 29, 2013 at 06:44

Hello Clive1,

Thanks for your interest. I agree your suggestions are possibilities, one of which may be what I will have to do. But what I really want to know at this point is whether Page 30 of the datasheet is correct where it seems to state the STM32F207xx has some specific feature to output a 25MHz or 50MHz clock for the PHY (as part of the MAC interface ?)  At least that's how I interpret page 30, so I would like to take advantage of this if it's available.  If the datasheet is wrong, or I've just miss-interpreted it, I would like to be sure about this, then I will certainly consider something else, probably a seperate 50MHz crystal for the PHY as you suggest, as I am committed to using the KS8721 which requires 50MHz for RMII mode. So, people's experience concerning the 50Mhz clock mentioned on page 30, or an official word from ST, would be very much appreciated. Thanks again, mai-au.

[Tesla DeLorean]

Posted on August 29, 2013 at 07:26

''The PHY is connected to the STM32F217xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F217xx.''

Like I said, the source of the clock is the MCO pin PA8, you should take a look at some Ethernet support code for examples.

GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIO clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
/* Enable SYSCFG clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure MCO (PA8) */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_MCO);
/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
// Or
/* Output PLL clock / 2 (50MHz) on MCO pin (PA8) to clock the PHY */
RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2); // PLL @ 100 MHz
You could also use MCO2 and PLLI2SCLK, say 150 MHz and Div 3

[martin]

Posted on August 30, 2013 at 02:47

Hello again Clive1 and others,

After further investigation and consideration, I have come to accept the datasheet is not saying there is a ''special'' 25Mhz or 50Mhz clock output associated with the MAC interface.  In fact in the diagram of a MII setup on page 164, it is the MCO signal that is providing the 25MHz clock, as you suggest. So it seems that using the MCO signal to output a 50MHz RMII clock is probably what page 30 of the datasheet intends, even if this isn't explained clearly (at least, it wasn't clear to me). But I have two reservations about this, which I would welcome opinions on.  First, I believe I have read that Ethernet clocks should not be provided via a PLL (too much jiitter ?) - I note in ST's example MII diagram on page 164 the 25MHz clock avoids the PLL... Second, if it is valid to use the PLL and MCO output to generate the 50MHz RMII clock, why does ST's example RMII diagram on page 164 show a seperate oscillator providing the 50MHz clock ? Any thoughts, recommendations or experience concerning these points would be appreciated. Thanking you, mai-au.

[Tesla DeLorean]

Posted on August 30, 2013 at 03:34

ST provides multiple ways to supply clocks on their boards, and use PHY's in MII and RMII modes. This permits experimentation. You should pick the clocking scheme that suits you, and your design/cost requirements.

Designs can share a common clock, you can divide down clocks. The F2 wants an external clock below 26 MHz The SMCS8720A for example can use a 25 MHz crystal

http://www.smsc.com/Products/Ethernet_and_Embedded_Networking/Ethernet_Transceivers/LAN8710A_LAN8720A

[martin]

Posted on August 30, 2013 at 04:03

Hello again Clive1,

Thanks for this info, though I am generally aware of the points you make.

The circuit I refer to is on Page 164 of the STM32F20xx general datasheet (see my original post), where I would think ST would want to make the STM32 look ''as capable as possible''.  On the same page there is an example circuit showing the STM32's MCO signal providing the 25MHz clock for a MII circuit, but in the RMII circuit they appear to suggest using an independent 50MHz oscillator to provide the RMII clock.  I am a bit concerned about this - is there a reason for this / does this matter... ?

Can you confirm the 50MHz MCO output technique has worked well for you ?  I guess the sample code you provided was from a known working system (in 50Mhz RMII mode) ?  I am committed to using the KS8721 PHY which requires 50MHz for RMII mode.  I already have a 25MHz clock provided to the STM32.

Thanks again for your continued interest.

mai-au.

[Tesla DeLorean]

Posted on August 30, 2013 at 05:35

You asked about how to get 25 and 50 MHz out, the code demonstrates that. You can measure the nature of the signal on any F2 design. Evaluate if the PLL introduces too much jitter, or if the thermal stability is where you need it.

I would imaging the reason to externalize the 50 MHz are three fold, one that it's probably not very power efficient to have the STM32 provide this clock, the 50 MHz is not coherent with the max speed of the processor, or peripheral set, causing the processor to run at a down-rated speed, or preclude the use of USB and/or I2S, and thirdly it limits the power-saving options on the STM32, if the clocks turn off you dump Ethernet connectivity.

[peterdonchev]

Posted on February 26, 2015 at 16:46

Sorry for digging up an old thread.

I'm planning to use STM32F407 with LAN8720 RMII PHY. I need more free space on the PCB and I want to eliminate PHY crystal. Is there something fundamentally wrong if I use PLLI2S to generate 50MHz clock on MCO2 pin and clock both MAC and PHY from there? STM32F407 will run at 168MHz from the main PLL.

[Tesla DeLorean]

Posted on February 26, 2015 at 17:50

I'd expect to work, but consume more power than the alternatives.

I will note that the 4-26 MHz limit is for a crystal. fHSE_ext is 1-50 MHz, ie XO, TCXO So if you have an external clock, have it be 50 MHz, and you can also feed that through the MCO pin, and have PLL_M be 50