ADC Sampling Rate for STM32G431: Practical vs Theoretical measurements

[krushna_moukthik]

Hello STM Community,

I am working with the STM32G431 microcontroller and have encountered a discrepancy between the practical and theoretical ADC sampling rates. Here's my setup:

• ADC Input: PA0 configured as ADC1_IN1 (single-ended mode).
• ADC Parameters:
  • Mode: IN1 Single Ended
  • ADC Prescaler: Synchronous Clock Mode Divided by 4
  • Resolution: 12 bits
  • Data Alignment: Right
  • Continuous Conversion Mode: Enabled
  • Sample Time: 2.4 ADC Cycles
• System Clock Frequency: 170 MHz

I have toggled a GPIO pin after ADC conversion to observe the sampling rate on an oscilloscope. The measured sampling rate is approximately 142 kHz, while my theoretical calculation suggests it should be around 11.33 MHz.

The theoretical calculation considers the formula:
Sampling Rate=fADC /{ [sampling time(in cycles)] + [resolution (in bits)] +(0.5)}​
Substituting the values:
Sampling Rate=170 MHz / (2.4+12+0.5)  ≈  11.33 MHz

I am unable to identify why there is such a significant difference between the calculated and observed rates. Could it be due to additional overhead, configuration issues, or something else I'm overlooking?

Any insights or suggestions to help resolve this would be greatly appreciated!

Thank you!

[krushna_moukthik]

Hi,

     I am currently working on configuring the ADC on the STM32G4 microcontroller, and I’ve encountered an issue where the observed sampling rate significantly differs from the expected values based on the calculations and settings. I am seeking reasons for this discrepancy and guidance to resolve it. I just want to know what error I have done in the following settings.

• Observations:

  • Observed sampling rate: 171.6 kHz.

  • Expected sampling rate based on calculation: 1.7 MHz [(170/4) MHz / (12.5 + 12.5 conversion cycles))

• Verified the system clock:

  • Used the MCO pin to output the main clock signal and confirmed the CPU is running at the expected frequency.

• Reviewed the ADC clock settings:

  • Ensured that the ADC module is receiving the configured clock frequency.(sampling time)

• Cross-referenced the ADC calculation formula:

  • Speed = ADC clock / (sampling cycles + conversion cycles).

  • For a 30 MHz clock and 12.5 sampling cycles, the expected rate aligns with 1.75 MHz.

Here's the code i have written

/* USER CODE BEGIN 2 */

HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);

HAL_ADC_Start_IT(&hadc1);

HAL_ADC_Stop_IT(&hadc1);

/* USER CODE END 2 */

/* USER CODE BEGIN 4 */

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {

HAL_ADC_GetValue(&hadc1); // Read the ADC value

HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_1); // Toggle GPIO for timing (PA1)

}

/* USER CODE END 4 */

[AScha.3]

Hi,

Seems you are not thinking about the time the CPU needs to do something: starting the ADC with an HAL call might need a microsecond or so, callback from an interrupt also, then add the time for your instructions there, and you see: impossible to get MHz speed for all this together.

So check it with a ADC speed of 10 kHz or lower, to see it working.

And If you want MHz speed, use the DMA to read a block of data at any speed, the ADC can do. This is the only way to get high speed conversion to the ram.

Or doing something else at high speed - data in or out- , the DMA is your friend .