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Undocumented Pullup on Pin PB4/JNRST



as I see it here in my test PCB, the pin PB4 (JNRST for JTAG interface) seems to have an internal weak pullup during reset (I assume 40kOhm as NRST - an external 10kOhm will pull this pin down, but 100kOhm pull down does NOT work...).

It is luckily "no real problem" in my application - but this is NOT mentioned anywhere in the datasheet - I think this should be somehow mentioned in the Datasheet, maybe chapter 7.3.16 "NRST pin characteristics", and also in the pin description table 7 (chapter 5) you possibly should write for PB4 "FT_pu" ("_pu" to signify this "weak pullup") instead of "FT").

My chip type here: STM32H750V (LPQFP100), Rev. V.

CORRECTION: Sorry, I found it now in the Reference Manual, chapter 10.3.1 ("GPIO), there it says that the debug pins JTDI (A!4) and NJTRST (B4) are in pull-up after reset... . But this info is a bit hidden, it would be nice to have this also somehow described in the pinning table and the NRST / Reset description of the datasheet. (I assume, that few people really use JTAG debug interface, most people like me presumably just will use 2wire debug SWCLK+SWDAT).

ST Employee

Hi @flyer31​ ,

For your PCB design, you need to refer to AN4938: Getting started with STM32H74xI/G and STM32H75xI/G hardware development.

You find there a dedicated section describing the debug port pins and details about "Internal pull-up and pull-down on JTAG pins":

  • NJTRST: internal pull-up
  • JTDI: internal pull-up
  • JTMS/SWDIO: internal pull-up
  • TCK/SWCLK: internal pull-down


To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Well assimilated this info.

Watch that the NRST doesn't fully reset the chip, several behaviours related to options, boot-up, power (LDO/SMPS) that seem to require physical power cycle

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