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STM32F401RE - ADC SMPRx 'sample time setting'

JohnBirchmeier
Associate II

Documentation Error? RM0368 sections 11.12.4 and 11.12.5 list sample A2D clock times for 8 different sample time settings. For all but setting 0, the data seem to disagree with my testing and performance measurements. My measurements indicate:

 

// SampleTime setting vs Conversion time in A2D Clocks (tested on board NUCLEO-F401RE):

// - CPU Clock = 84 MHz

// - A2D Clock Pre-scaler = 2

// - Three channels per scan (ADC IN0, IN1 & IN4) with DMA transfer ADC to memory.

//

// 0 => 12.5 + 2.5 = 15 A2D Clocks / convert ( 3M conversions in 1.0714 s) << ONLY real match to general document a 15 clocks = (3 + 12)

// 1 => 12.5 + 10.5 = 23 A2D Clocks / convert ( 3M conversions in 1.6427 s)

// 2 => 12.5 + 19.2 = 31.7 ... ??? very odd (30M conversions in 22.6189s)

// 3 => 12.5 + 28.5 = 41 A2D Clocks / convert (30M conversions in 29.2856s)

// 4 => 12.5 + 56.5 = 69 A2D Clocks / convert (30M conversions in 49.2855s)

// 5 => 12.5 + 75.1 = 87.6 ... ??? very odd (30M conversions in 62.6187s)

// 6 => 12.5 + 96.5 = 109 A2D Clocks / convert (30M conversions in 77.8568s)

// 7 => 12.5 + 320.5 = 333 A2D Clocks / convert (30M conversions in 237.8558s)

//

 

1 ACCEPTED SOLUTION

Accepted Solutions
TDK
Super User

> (ADC IN0, IN1 & IN4)

You have channel 4 sample rate (SMP4) unchanged. Setting up SMP2 affects channel 2 (IN2).

If you feel a post has answered your question, please click "Accept as Solution".

View solution in original post

9 REPLIES 9
TDK
Super User

Interesting that you're measuring less than the expected time, and not more. How are you measuring these durations exactly? I've done the same on STM32F429 (or maybe F405/F411) and they matched the RM exactly. I suspect it's the same ADC module on all of them.

(Note that conversion time is 12 cycles exactly, not 12.5.)

If you feel a post has answered your question, please click "Accept as Solution".

I have a 10KHz timer. I grab the value at the start of the DMA and grab the time again from within the DMA callback and I hit 10 million scans (i.e. 30 million A2D conversions complete).

I also verified the 10KHz timer operation by dumping its value to the console every 10s and used a stop watch to verify that timer is accurate.

JohnBirchmeier
Associate II

NOTE: I just noticed that I have set the ADC clock pre-scaler set to 2, whereas the Device Configuration Took will only allow a setting of [4, 6 or 8]. Perhaps I'm violating some rule here ... I'll update my code and retest.

So you have a DMA conversion complete every 3 samples? So every 1us at the lowest sample rate? Doesn't seem like the code would be able to keep up with that.

If you feel a post has answered your question, please click "Accept as Solution".
JohnBirchmeier
Associate II

The DMA completes after 300 conversions (i.e. 100 scans of 3 channels). The DMA is configurated for continuous requests with callbacks for 1/2 complete and complete.

Do you want me to strip down my test code and send you a copy? Do you have access to the NUCLEO-F401RE board on which to test (or something similar)?

waclawek.jan
Super User

You've changed sampling time for only 2 of the 3 ADC channels, the 3rd remained at 0 i.e. 3 cycles for sampling (or 2.5, depending on which table are you looking at).

JW

I think I have all three channels set the same sampling time setting. For example, for setting 1, this is the ADC1->SMPR2 (offset 0x10) register value before the DMA starts and the value is unaltered when it stop. See image:

ADC1 offset 0x10 set to 0x49 (i.e. all three channels are configured for '1')ADC1 offset 0x10 set to 0x49 (i.e. all three channels are configured for '1')

 

 

TDK
Super User

> (ADC IN0, IN1 & IN4)

You have channel 4 sample rate (SMP4) unchanged. Setting up SMP2 affects channel 2 (IN2).

If you feel a post has answered your question, please click "Accept as Solution".

You were right, I just could not see the issue.