SPI for 33 bits frame size

[GeethaAndrew]

I am using STM32H745 MCU. 
My requirement is to receive 33 bits of data on SPI in slave mode. 
The master transmits 33 clocks. 
It is not possible to split the data as reconfiguration of SPI in between the clocks is difficult. 

Is there a way to read partially filled SPI data register? 

If I know the end of 33 clocks, and if the configure the data size is 32 bits, at the end of 33 clocks I can read 32 bits from the FIFO. 
The last 1 bit which will be available in the data register is to be read. The data register data doesn’t go to the FIFO for reading until 32 bits are received. 

How to resolve this issue?

[MasterT · Accepted solution]

Probably, you can configure SPI to receive 3 words 11-bits each. DMA would store them as 16-bits half-word triplets. Later CPU can run through receive buffer to extract 3x 11-bits back from 3x uint16_t,  and shifting  |= & combine into single uint64_t

[GeethaAndrew]

I agree, for 33 bits, I can do this way.

But, I want to write a generalized application wherein the number of bits to be received varies at different instances.

It could be a prime number and above 32 bit.(Ex. 37 bits).

[MasterT]

Just an idea using 2x SPI and Timer. I'd configure timer to external clock (master-SCLK) and 2 PWM output. Timer counts arriving train of 37 clock, than at 32-nd produces two anti-phase PWM for 2 SPI in slave mode. One SPI has CS from TIM and stops operation, and another just starts. At the end would be 32-bits and N-bits in two buffers that easily to re-assemble back. SCLK and SDI connected to both SPI as usual. Max 64-bits,  TIM likely to have one more reset input from master-CS - not to lost sync in case of interference on the bus