NUCLEO-G474RE ADC Clock

[tomm5771]

I have a couple of questions regarding the ADC clock on the board in the subject.

What is the default clock speed and where is the clock configured?

All I see in the documentation is that the clock is independent from the AHB clock, but I don't see where it is actually configured.

Also, the ClockPrescaler lets me choose between Synchronous and Asynchronous. What is the difference in this context. Is synchronous referring to the main system clock?

[AScha.3]

see rm:

> choose between Synchronous and Asynchronous

Sync = to the AHB bus , its connected to; Async = the ADC clk in clock tree , you can set.

>I don't see where it is actually configured.

You should see in CubeMX, what you choose. 🙂

>What is the default clock speed

---> read ds, max. clk is there; what you set it then, is up to you - or what you need.

[tomm5771]

Is the ADC clock the same thing as the sampling rate?

[AScha.3]

No no .

Read in rm ...

ADC clk is needed to run the ADC at all, up to the maximum clk, see ds for this and your cpu.

Sampling rate then is to adjust the sampling time (for every input possible) and if /how often you call it to convert,

-> giving the effective saple rate..

Or use a timer -> to get a certain fixed sample rate (and store data by DMA).

[tomm5771]

Say for instance that I set the ADC to trigger on a timer. I see there is something referring to "clock cycle" in the reference manual. Would clock cycle refer to the ADC clock or one cycle for the timer that you have set?

[AScha.3]

The ADC ...rtfm... needs some 12+(sampling time) clocks for a conversion (<- the ADC clock) ;

one trigger/start -> one conversion (or sequence of ..- what you set, he will do).

Every conversion needs some time - depending, on what you set (clock , sampling time, sequence..),

then result is ready (you or DMA has to read it) and it can do the next conversion...if you want.

[tomm5771]

Yes I see that in the manual if I want to get 12 bit resolution, 12.5 clock cycles are required. I also have the sampling time set to 247.5 cycles.

What I am really confused about is this. I have the ADC set to an external trigger at timer 3, which gets triggered every 1 millisecond. Does this mean that the ADC will start a new sample every millisecond, and that it will take 12.5 + 247.5 clock cycles of the ADC_CLOCK to complete 1 conversion? I have the ADC_CLOCK set to 42.5 MHz, so (12.5 + 247.5) * (1/42500000) = 6.12 μsec. So it should take 6.12 μsec to do one conversion every millisecond?

[AScha.3]

Right - now you understand it . 🙂